[llvm] r242732 - AArch64: Restrict macroop fusion heuristics to cyclone.

[Matthias Braun]

Author: matze
Date: Mon Jul 20 18:11:42 2015
New Revision: 242732

URL: http://llvm.org/viewvc/llvm-project?rev=242732&view=rev
Log:
AArch64: Restrict macroop fusion heuristics to cyclone.

Even though this is just some hinting for the scheduler it doesn't make
sense to do that unless you know the target can perform the fusion.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=242732&r1=242731&r2=242732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Mon Jul 20 18:11:42 2015
@@ -1445,38 +1445,40 @@ bool AArch64InstrInfo::shouldClusterLoad
 
 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
                                               MachineInstr *Second) const {
-  // Cyclone can fuse CMN, CMP, TST followed by Bcc.
-  unsigned SecondOpcode = Second->getOpcode();
-  if (SecondOpcode == AArch64::Bcc) {
-    switch (First->getOpcode()) {
-    default:
-      return false;
-    case AArch64::SUBSWri:
-    case AArch64::ADDSWri:
-    case AArch64::ANDSWri:
-    case AArch64::SUBSXri:
-    case AArch64::ADDSXri:
-    case AArch64::ANDSXri:
-      return true;
+  if (Subtarget.isCyclone()) {
+    // Cyclone can fuse CMN, CMP, TST followed by Bcc.
+    unsigned SecondOpcode = Second->getOpcode();
+    if (SecondOpcode == AArch64::Bcc) {
+      switch (First->getOpcode()) {
+      default:
+        return false;
+      case AArch64::SUBSWri:
+      case AArch64::ADDSWri:
+      case AArch64::ANDSWri:
+      case AArch64::SUBSXri:
+      case AArch64::ADDSXri:
+      case AArch64::ANDSXri:
+        return true;
+      }
     }
-  }
-  // Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
-  if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
-      SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
-    switch (First->getOpcode()) {
-    default:
-      return false;
-    case AArch64::ADDWri:
-    case AArch64::ADDXri:
-    case AArch64::ANDWri:
-    case AArch64::ANDXri:
-    case AArch64::EORWri:
-    case AArch64::EORXri:
-    case AArch64::ORRWri:
-    case AArch64::ORRXri:
-    case AArch64::SUBWri:
-    case AArch64::SUBXri:
-      return true;
+    // Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
+    if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
+        SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
+      switch (First->getOpcode()) {
+      default:
+        return false;
+      case AArch64::ADDWri:
+      case AArch64::ADDXri:
+      case AArch64::ANDWri:
+      case AArch64::ANDXri:
+      case AArch64::EORWri:
+      case AArch64::EORXri:
+      case AArch64::ORRWri:
+      case AArch64::ORRXri:
+      case AArch64::SUBWri:
+      case AArch64::SUBXri:
+        return true;
+      }
     }
   }
   return false;