[PATCH] D11359: [AArch64] Change EON pattern to match more often.

[Geoff Berry]

gberry created this revision.
gberry added reviewers: jmolloy, t.p.northover.
gberry added subscribers: llvm-commits, mcrosier.
Herald added subscribers: rengolin, aemerson.

Change EON pattern to match pattern after DAG reassociation.

Fixes bug PR22751 (https://llvm.org/bugs/show_bug.cgi?id=22751).

http://reviews.llvm.org/D11359

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/eon.ll

Index: test/CodeGen/AArch64/eon.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/eon.ll
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+
+; Check that the eon instruction is generated instead of eor,movn
+define i64 @f(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f
+; CHECK: eon
+; CHECK: ret
+entry:
+  %shl = shl i64 %b, 4
+  %neg = xor i64 %a, -1
+  %xor = xor i64 %shl, %neg
+  ret i64 %xor
+}
+
+; Same check with mutliple uses of %neg
+define i64 @f2(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f2
+; CHECK: eon
+; CHECK: eon
+; CHECK: lsl
+; CHECK: ret
+entry:
+  %shl = shl i64 %b, 4
+  %neg = xor i64 %shl, -1
+  %xor = xor i64 %neg, %a
+  %xor1 = xor i64 %c, %neg
+  %shl2 = shl i64 %xor, %xor1
+  ret i64 %shl2
+}
+
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -841,7 +841,7 @@
 defm BIC  : LogicalReg<0b00, 1, "bic",
                        BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
 defm EON  : LogicalReg<0b10, 1, "eon",
-                       BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
+                       BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
 defm EOR  : LogicalReg<0b10, 0, "eor", xor>;
 defm ORN  : LogicalReg<0b01, 1, "orn",
                        BinOpFrag<(or node:$LHS, (not node:$RHS))>>;


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