[PATCH] D10683: AVX-512 vector shuffle lowering

[Ayal Zaks]

Ayal added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:10084
@@ +10083,3 @@
+    VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
+                        DAG.getConstant(Mask[i], DL,MaskEltVT));
+  SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
----------------
Missing space "DL,MaskEltVT"

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:10113
@@ -10139,1 +10112,3 @@
+    return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
 
+  return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
----------------
You may want to check isSingleInputShuffleMask() here, and call either lowerVectorShuffleWithPERMV() or lowerVectorShuffleWithPERMV3(?) accordingly.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:10198
@@ -10223,3 +10197,3 @@
 
   // Dispatch to each element type for lowering. If we don't have supprot for
   // specific element type shuffles at 512 bits, immediately split them and
----------------
typo in original code: supprot


Repository:
  rL LLVM

http://reviews.llvm.org/D10683