[llvm] r242442 - [PowerPC] v4i32 is a VSRCRegClass
Hal Finkel
hfinkel at anl.gov
Thu Jul 16 14:37:04 PDT 2015
Hi Hans,
I approve pulling this into the release branch.
Thanks again,
Hal
----- Original Message -----
> From: "Bill Schmidt" <wschmidt at linux.vnet.ibm.com>
> To: llvm-commits at cs.uiuc.edu
> Sent: Thursday, July 16, 2015 4:14:08 PM
> Subject: [llvm] r242442 - [PowerPC] v4i32 is a VSRCRegClass
>
> Author: wschmidt
> Date: Thu Jul 16 16:14:07 2015
> New Revision: 242442
>
> URL: http://llvm.org/viewvc/llvm-project?rev=242442&view=rev
> Log:
> [PowerPC] v4i32 is a VSRCRegClass
>
> I was looking at some vector code generation and kept seeing
> unnecessary vector copies into the Altivec half of the VSX registers.
> I discovered that we overlooked v4i32 when adding the register
> classes
> for VSX; we only added v4f32 and v2f64. This means that anything
> that
> canonicalizes into v4i32 (which is a LOT of stuff) ends up being
> forced into VRRC on its way to VSRC.
>
> The fix is one line. The rest of the patch is fixing up some test
> cases whose code generation has changed as a result.
>
> This seems like it would be a good candidate for backport to 3.7.
>
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/test/CodeGen/PowerPC/vsx.ll
> llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=242442&r1=242441&r2=242442&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jul 16
> 16:14:07 2015
> @@ -580,6 +580,7 @@ PPCTargetLowering::PPCTargetLowering(con
>
> addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
>
> + addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
> addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
> addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
>
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/vsx.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx.ll?rev=242442&r1=242441&r2=242442&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/vsx.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/vsx.ll Thu Jul 16 16:14:07 2015
> @@ -70,10 +70,10 @@ entry:
> ; CHECK-REG: blr
>
> ; CHECK-FISL-LABEL: @test5
> -; CHECK-FISL: vor 4, 2, 2
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: xxlxor 36, 36, 37
> -; CHECK-FISL: vor 2, 4, 4
> +; CHECK-FISL: vor
> +; CHECK-FISL: vor
> +; CHECK-FISL: xxlxor
> +; CHECK-FISL: vor 2
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test5
> @@ -133,10 +133,10 @@ entry:
> ; CHECK-REG: blr
>
> ; CHECK-FISL-LABEL: @test8
> -; CHECK-FISL: vor 4, 2, 2
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: xxlor 36, 36, 37
> -; CHECK-FISL: vor 2, 4, 4
> +; CHECK-FISL: vor
> +; CHECK-FISL: vor
> +; CHECK-FISL: xxlor
> +; CHECK-FISL: vor 2
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test8
> @@ -196,10 +196,10 @@ entry:
> ; CHECK-REG: blr
>
> ; CHECK-FISL-LABEL: @test11
> -; CHECK-FISL: vor 4, 2, 2
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: xxland 36, 36, 37
> -; CHECK-FISL: vor 2, 4, 4
> +; CHECK-FISL: vor
> +; CHECK-FISL: vor
> +; CHECK-FISL: xxland
> +; CHECK-FISL: vor 2
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test11
> @@ -260,17 +260,14 @@ entry:
> ; CHECK-REG: blr
>
> ; CHECK-FISL-LABEL: @test14
> -; CHECK-FISL: vor 4, 2, 2
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: xxlor 36, 36, 37
> -; CHECK-FISL: vor 0, 4, 4
> -; CHECK-FISL: vor 4, 2, 2
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: xxlnor 36, 36, 37
> +; CHECK-FISL: vor 4, 3, 3
> +; CHECK-FISL: vor 5, 2, 2
> +; CHECK-FISL: xxlor 0, 37, 36
> +; CHECK-FISL: xxlnor 36, 37, 36
> ; CHECK-FISL: vor 2, 4, 4
> ; CHECK-FISL: lis 0, -1
> ; CHECK-FISL: ori 0, 0, 65520
> -; CHECK-FISL: stvx 0, 1, 0
> +; CHECK-FISL: stxvd2x 0, 1, 0
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test14
> @@ -347,15 +344,13 @@ entry:
> ; CHECK-REG: blr
>
> ; CHECK-FISL-LABEL: @test17
> -; CHECK-FISL: vspltisb 4, -1
> -; CHECK-FISL: vor 5, 3, 3
> -; CHECK-FISL: vor 0, 4, 4
> -; CHECK-FISL: xxlxor 37, 37, 32
> -; CHECK-FISL: vor 3, 5, 5
> +; CHECK-FISL: vor 4, 3, 3
> ; CHECK-FISL: vor 5, 2, 2
> -; CHECK-FISL: vor 0, 3, 3
> -; CHECK-FISL: xxland 37, 37, 32
> -; CHECK-FISL: vor 2, 5, 5
> +; CHECK-FISL: vspltisb 2, -1
> +; CHECK-FISL: vor 0, 2, 2
> +; CHECK-FISL: xxlxor 36, 36, 32
> +; CHECK-FISL: xxland 36, 37, 36
> +; CHECK-FISL: vor 2, 4, 4
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test17
> @@ -434,12 +429,18 @@ entry:
> ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
> ; CHECK-REG: blr
>
> +; FIXME: The fast-isel code is pretty miserable for this one.
> +
> ; CHECK-FISL-LABEL: @test20
> -; CHECK-FISL: vcmpequw 4, 4, 5
> -; CHECK-FISL: vor 0, 3, 3
> -; CHECK-FISL: vor 1, 2, 2
> -; CHECK-FISL: vor 6, 4, 4
> -; CHECK-FISL: xxsel 32, 32, 33, 38
> +; CHECK-FISL: vor 0, 5, 5
> +; CHECK-FISL: vor 1, 4, 4
> +; CHECK-FISL: vor 6, 3, 3
> +; CHECK-FISL: vor 7, 2, 2
> +; CHECK-FISL: vor 2, 1, 1
> +; CHECK-FISL: vor 3, 0, 0
> +; CHECK-FISL: vcmpequw 2, 2, 3
> +; CHECK-FISL: vor 0, 2, 2
> +; CHECK-FISL: xxsel 32, 38, 39, 32
> ; CHECK-FISL: vor 2, 0, 0
> ; CHECK-FISL: blr
>
> @@ -794,8 +795,6 @@ define <4 x i32> @test34(<4 x i32>* %a)
> ; CHECK-FISL-LABEL: @test34
> ; CHECK-FISL: lxvw4x 0, 0, 3
> ; CHECK-FISL: xxlor 34, 0, 0
> -; CHECK-FISL: vor 3, 2, 2
> -; CHECK-FISL: vor 2, 3, 3
> ; CHECK-FISL: blr
>
> ; CHECK-LE-LABEL: @test34
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll?rev=242442&r1=242441&r2=242442&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
> (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll Thu Jul
> 16 16:14:07 2015
> @@ -8,9 +8,9 @@ define <2 x double> @testi0(<2 x double>
>
> ; CHECK-LABEL: testi0
> ; CHECK: lxvd2x 0, 0, 3
> -; CHECK: lxsdx 34, 0, 4
> +; CHECK: lxsdx 1, 0, 4
> ; CHECK: xxswapd 0, 0
> -; CHECK: xxspltd 1, 34, 0
> +; CHECK: xxspltd 1, 1, 0
> ; CHECK: xxpermdi 34, 0, 1, 1
> }
>
> @@ -22,9 +22,9 @@ define <2 x double> @testi1(<2 x double>
>
> ; CHECK-LABEL: testi1
> ; CHECK: lxvd2x 0, 0, 3
> -; CHECK: lxsdx 34, 0, 4
> +; CHECK: lxsdx 1, 0, 4
> ; CHECK: xxswapd 0, 0
> -; CHECK: xxspltd 1, 34, 0
> +; CHECK: xxspltd 1, 1, 0
> ; CHECK: xxmrgld 34, 1, 0
> }
>
>
>
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--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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