[PATCH] D11224: SelectionDAG: Add AssertAnd SDNode

[escha]

escha added a comment.

If I'm understanding right, this is distinct from (for example) the concept behind the code in AARCH64 that calls simplifyDemandedBits on addresses used by loads/stores to optimize given knowledge of 56-bit addresses? That is, this node represents "the high bits must be zero", not "the high bits are ignored by the addressing operations" (also, is there some reason this can't use AssertZext -- is it because AssertZext can't take an i48?)


http://reviews.llvm.org/D11224