[llvm] r242204 - MIR Serialization: Serialize the machine basic block live in registers.
Alex Lorenz
arphaman at gmail.com
Tue Jul 14 14:24:42 PDT 2015
Author: arphaman
Date: Tue Jul 14 16:24:41 2015
New Revision: 242204
URL: http://llvm.org/viewvc/llvm-project?rev=242204&view=rev
Log:
MIR Serialization: Serialize the machine basic block live in registers.
Added:
llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=242204&r1=242203&r2=242204&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue Jul 14 16:24:41 2015
@@ -102,9 +102,9 @@ struct MachineBasicBlock {
unsigned Alignment = 0;
bool IsLandingPad = false;
bool AddressTaken = false;
- // TODO: Serialize the successor weights and liveins.
+ // TODO: Serialize the successor weights.
std::vector<FlowStringValue> Successors;
-
+ std::vector<FlowStringValue> LiveIns;
std::vector<StringValue> Instructions;
};
@@ -117,6 +117,7 @@ template <> struct MappingTraits<Machine
YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
YamlIO.mapOptional("successors", MBB.Successors);
+ YamlIO.mapOptional("liveins", MBB.LiveIns);
YamlIO.mapOptional("instructions", MBB.Instructions);
}
};
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=242204&r1=242203&r2=242204&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Tue Jul 14 16:24:41 2015
@@ -78,6 +78,7 @@ public:
bool parse(MachineInstr *&MI);
bool parseMBB(MachineBasicBlock *&MBB);
+ bool parseNamedRegister(unsigned &Reg);
bool parseRegister(unsigned &Reg);
bool parseRegisterFlag(unsigned &Flags);
@@ -215,6 +216,18 @@ bool MIParser::parseMBB(MachineBasicBloc
return false;
}
+bool MIParser::parseNamedRegister(unsigned &Reg) {
+ lex();
+ if (Token.isNot(MIToken::NamedRegister))
+ return error("expected a named register");
+ if (parseRegister(Reg))
+ return 0;
+ lex();
+ if (Token.isNot(MIToken::Eof))
+ return error("expected end of string after the register reference");
+ return false;
+}
+
static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
assert(MO.isImplicit());
return MO.isDef() ? "implicit-def" : "implicit";
@@ -583,3 +596,11 @@ bool llvm::parseMBBReference(MachineBasi
const SlotMapping &IRSlots, SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);
}
+
+bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
+ MachineFunction &MF, StringRef Src,
+ const PerFunctionMIParsingState &PFS,
+ const SlotMapping &IRSlots,
+ SMDiagnostic &Error) {
+ return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
+}
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=242204&r1=242203&r2=242204&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h Tue Jul 14 16:24:41 2015
@@ -40,6 +40,12 @@ bool parseMBBReference(MachineBasicBlock
const PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots, SMDiagnostic &Error);
+bool parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
+ MachineFunction &MF, StringRef Src,
+ const PerFunctionMIParsingState &PFS,
+ const SlotMapping &IRSlots,
+ SMDiagnostic &Error);
+
} // end namespace llvm
#endif
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=242204&r1=242203&r2=242204&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Jul 14 16:24:41 2015
@@ -321,6 +321,14 @@ bool MIRParserImpl::initializeMachineBas
// TODO: Report an error when adding the same successor more than once.
MBB.addSuccessor(SuccMBB);
}
+ // Parse the liveins.
+ for (const auto &LiveInSource : YamlMBB.LiveIns) {
+ unsigned Reg = 0;
+ if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,
+ IRSlots, Error))
+ return error(Error, LiveInSource.SourceRange);
+ MBB.addLiveIn(Reg);
+ }
// Parse the instructions.
for (const auto &MISource : YamlMBB.Instructions) {
MachineInstr *MI = nullptr;
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=242204&r1=242203&r2=242204&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Jul 14 16:24:41 2015
@@ -233,7 +233,15 @@ void MIRPrinter::convert(ModuleSlotTrack
MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
YamlMBB.Successors.push_back(StrOS.str());
}
-
+ // Print the live in registers.
+ const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
+ assert(TRI && "Expected target register info");
+ for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
+ std::string Str;
+ raw_string_ostream StrOS(Str);
+ printReg(*I, StrOS, TRI);
+ YamlMBB.LiveIns.push_back(StrOS.str());
+ }
// Print the machine instructions.
YamlMBB.Instructions.reserve(MBB.size());
std::string Str;
Added: llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir?rev=242204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir Tue Jul 14 16:24:41 2015
@@ -0,0 +1,25 @@
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses basic block liveins correctly.
+
+--- |
+
+ define i32 @test(i32 %a, i32 %b) {
+ body:
+ %c = add i32 %a, %b
+ ret i32 %c
+ }
+
+...
+---
+name: test
+body:
+ # CHECK: name: body
+ # CHECK: liveins: [ '%edi', '%esi' ]
+ # CHECK-NEXT: instructions:
+ - id: 0
+ name: body
+ liveins: [ '%edi', '%esi' ]
+ instructions:
+ - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
+ - 'RETQ %eax'
+...
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir?rev=242204&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir Tue Jul 14 16:24:41 2015
@@ -0,0 +1,21 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define i32 @test(i32 %a) {
+ body:
+ ret i32 %a
+ }
+
+...
+---
+name: test
+body:
+ - id: 0
+ name: body
+ # CHECK: [[@LINE+1]]:21: expected a named register
+ liveins: [ '%0' ]
+ instructions:
+ - '%eax = COPY %edi'
+ - 'RETQ %eax'
+...
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