[llvm] r242084 - MIR Serialization: Serialize the sub register indices.
Alex Lorenz
arphaman at gmail.com
Mon Jul 13 16:24:35 PDT 2015
Author: arphaman
Date: Mon Jul 13 18:24:34 2015
New Revision: 242084
URL: http://llvm.org/viewvc/llvm-project?rev=242084&view=rev
Log:
MIR Serialization: Serialize the sub register indices.
This commit serializes the sub register indices from the register machine
operands.
Reviewers: Duncan P. N. Exon Smith
Added:
llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
Modified:
llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=242084&r1=242083&r2=242084&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Mon Jul 13 18:24:34 2015
@@ -179,6 +179,8 @@ static MIToken::TokenKind symbolToken(ch
return MIToken::comma;
case '=':
return MIToken::equal;
+ case ':':
+ return MIToken::colon;
default:
return MIToken::Error;
}
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=242084&r1=242083&r2=242084&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Mon Jul 13 18:24:34 2015
@@ -35,6 +35,7 @@ struct MIToken {
comma,
equal,
underscore,
+ colon,
// Keywords
kw_implicit,
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=242084&r1=242083&r2=242084&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Mon Jul 13 18:24:34 2015
@@ -56,6 +56,8 @@ class MIParser {
StringMap<unsigned> Names2Regs;
/// Maps from register mask names to register masks.
StringMap<const uint32_t *> Names2RegMasks;
+ /// Maps from subregister names to subregister indices.
+ StringMap<unsigned> Names2SubRegIndices;
public:
MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
@@ -79,6 +81,7 @@ public:
bool parseRegister(unsigned &Reg);
bool parseRegisterFlag(unsigned &Flags);
+ bool parseSubRegisterIndex(unsigned &SubReg);
bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
bool parseImmediateOperand(MachineOperand &Dest);
bool parseMBBReference(MachineBasicBlock *&MBB);
@@ -115,6 +118,13 @@ private:
///
/// Return null if the identifier isn't a register mask.
const uint32_t *getRegMask(StringRef Identifier);
+
+ void initNames2SubRegIndices();
+
+ /// Check if the given identifier is a name of a subregister index.
+ ///
+ /// Return 0 if the name isn't a subregister index class.
+ unsigned getSubRegIndex(StringRef Name);
};
} // end anonymous namespace
@@ -332,6 +342,19 @@ bool MIParser::parseRegisterFlag(unsigne
return false;
}
+bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
+ assert(Token.is(MIToken::colon));
+ lex();
+ if (Token.isNot(MIToken::Identifier))
+ return error("expected a subregister index after ':'");
+ auto Name = Token.stringValue();
+ SubReg = getSubRegIndex(Name);
+ if (!SubReg)
+ return error(Twine("use of unknown subregister index '") + Name + "'");
+ lex();
+ return false;
+}
+
bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
unsigned Reg;
unsigned Flags = IsDef ? RegState::Define : 0;
@@ -344,10 +367,15 @@ bool MIParser::parseRegisterOperand(Mach
if (parseRegister(Reg))
return true;
lex();
- // TODO: Parse subregister.
+ unsigned SubReg = 0;
+ if (Token.is(MIToken::colon)) {
+ if (parseSubRegisterIndex(SubReg))
+ return true;
+ }
Dest = MachineOperand::CreateReg(
Reg, Flags & RegState::Define, Flags & RegState::Implicit,
- Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef);
+ Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
+ /*isEarlyClobber=*/false, SubReg);
return false;
}
@@ -525,6 +553,23 @@ const uint32_t *MIParser::getRegMask(Str
return RegMaskInfo->getValue();
}
+void MIParser::initNames2SubRegIndices() {
+ if (!Names2SubRegIndices.empty())
+ return;
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ for (unsigned I = 1, E = TRI->getNumSubRegIndices(); I < E; ++I)
+ Names2SubRegIndices.insert(
+ std::make_pair(StringRef(TRI->getSubRegIndexName(I)).lower(), I));
+}
+
+unsigned MIParser::getSubRegIndex(StringRef Name) {
+ initNames2SubRegIndices();
+ auto SubRegInfo = Names2SubRegIndices.find(Name);
+ if (SubRegInfo == Names2SubRegIndices.end())
+ return 0;
+ return SubRegInfo->getValue();
+}
+
bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,
MachineFunction &MF, StringRef Src,
const PerFunctionMIParsingState &PFS,
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=242084&r1=242083&r2=242084&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Mon Jul 13 18:24:34 2015
@@ -303,7 +303,9 @@ void MIPrinter::print(const MachineOpera
if (Op.isUndef())
OS << "undef ";
printReg(Op.getReg(), OS, TRI);
- // TODO: Print sub register.
+ // Print the sub register.
+ if (Op.getSubReg() != 0)
+ OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
break;
case MachineOperand::MO_Immediate:
OS << Op.getImm();
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir?rev=242084&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir Mon Jul 13 18:24:34 2015
@@ -0,0 +1,29 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define zeroext i1 @t(i1 %c) {
+ entry:
+ ret i1 %c
+ }
+
+...
+---
+name: t
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr8 }
+ - { id: 2, class: gr8 }
+body:
+ - name: entry
+ id: 0
+ instructions:
+ - '%0 = COPY %edi'
+ # CHECK: [[@LINE+1]]:25: expected a subregister index after ':'
+ - '%1 = COPY %0 : 42'
+ - '%2 = AND8ri %1, 1, implicit-def %eflags'
+ - '%al = COPY %2'
+ - 'RETQ %al'
+...
Added: llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir?rev=242084&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir Mon Jul 13 18:24:34 2015
@@ -0,0 +1,33 @@
+# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses subregisters in register operands
+# correctly.
+
+--- |
+
+ define zeroext i1 @t(i1 %c) {
+ entry:
+ ret i1 %c
+ }
+
+...
+---
+name: t
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr8 }
+ - { id: 2, class: gr8 }
+body:
+ - name: entry
+ id: 0
+ instructions:
+ # CHECK: %0 = COPY %edi
+ # CHECK-NEXT: %1 = COPY %0:sub_8bit
+ - '%0 = COPY %edi'
+ - '%1 = COPY %0:sub_8bit'
+ - '%2 = AND8ri %1, 1, implicit-def %eflags'
+ - '%al = COPY %2'
+ - 'RETQ %al'
+...
+
Added: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir?rev=242084&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir Mon Jul 13 18:24:34 2015
@@ -0,0 +1,31 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when an unknown subregister index
+# is encountered.
+
+--- |
+
+ define zeroext i1 @t(i1 %c) {
+ entry:
+ ret i1 %c
+ }
+
+...
+---
+name: t
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr8 }
+ - { id: 2, class: gr8 }
+body:
+ - name: entry
+ id: 0
+ instructions:
+ - '%0 = COPY %edi'
+ # CHECK: [[@LINE+1]]:23: use of unknown subregister index 'bit8'
+ - '%1 = COPY %0:bit8'
+ - '%2 = AND8ri %1, 1, implicit-def %eflags'
+ - '%al = COPY %2'
+ - 'RETQ %al'
+...
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