[PATCH] D11126: Add support for nest attribute to ARM backend

[Stephen Cross]

scross99 created this revision.
scross99 added a reviewer: asl.
scross99 added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

The nest attribute is currently supported on the x86 (32-bit), x86-64, PowerPC and AArch64 backends, but not on ARM (32-bit). This patch adds support for nest to the ARM backend.

Register r12 is used by GCC for this purpose (see https://github.com/gcc-mirror/gcc/blob/7c62dfbbcd3699efcbbadc9fb3aa14f23a123add/gcc/testsuite/gcc.dg/cwsc1.c ) and hence is used here. As discussed on the GCC mailing list (see http://www.mail-archive.com/gcc@gcc.gnu.org/msg76966.html ) the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible.

Relevant LLVM mailing list discussion: http://comments.gmane.org/gmane.comp.compilers.llvm.devel/86370

http://reviews.llvm.org/D11126

Files:
  lib/Target/ARM/ARMCallingConv.td
  test/CodeGen/ARM/nest-register.ll

Index: test/CodeGen/ARM/nest-register.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/nest-register.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+
+; Tests that the 'nest' parameter attribute causes the relevant parameter to be
+; passed in the right register.
+
+define i8* @nest_receiver(i8* nest %arg) nounwind {
+; CHECK-LABEL: nest_receiver:
+; CHECK: @ BB#0:
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: mov pc, lr
+        ret i8* %arg
+}
+
+define i8* @nest_caller(i8* %arg) nounwind {
+; CHECK-LABEL: nest_caller:
+; CHECK: mov r12, r0
+; CHECK-NEXT: bl nest_receiver
+; CHECK: mov pc, lr
+        %result = call i8* @nest_receiver(i8* nest %arg)
+        ret i8* %result
+}
Index: lib/Target/ARM/ARMCallingConv.td
===================================================================
--- lib/Target/ARM/ARMCallingConv.td
+++ lib/Target/ARM/ARMCallingConv.td
@@ -142,6 +142,9 @@
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
+  // The 'nest' parameter, if any, is passed in R12.
+  CCIfNest<CCAssignToReg<[R12]>>,
+
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,


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