[PATCH] D10981: MIR Serialization: serialize the virtual register definitions.

[Duncan P. N. Exon Smith]

> On 2015-Jul-09, at 12:59, Alex Lorenz <arphaman at gmail.com> wrote:
> 
> arphaman updated this revision to Diff 29375.
> arphaman added a comment.
> 
> I've rebased this patch on ToT.
> 
> 
> Repository:
>  rL LLVM
> 
> http://reviews.llvm.org/D10981
> 
> Files:
>  include/llvm/CodeGen/MIRYamlMapping.h
>  lib/CodeGen/MIRParser/MIRParser.cpp
>  lib/CodeGen/MIRPrinter.cpp
>  test/CodeGen/MIR/X86/undefined-register-class.mir
>  test/CodeGen/MIR/X86/virtual-registers.mir
> 
> <D10981.29375.patch>

> Index: lib/CodeGen/MIRParser/MIRParser.cpp
> ===================================================================
> --- lib/CodeGen/MIRParser/MIRParser.cpp
> +++ lib/CodeGen/MIRParser/MIRParser.cpp
> @@ -315,14 +326,27 @@
>  }
>  
>  bool MIRParserImpl::initializeRegisterInfo(
> -    MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
> +    const MachineFunction &MF, MachineRegisterInfo &RegInfo,
> +    const yaml::MachineFunction &YamlMF) {
>    assert(RegInfo.isSSA());
>    if (!YamlMF.IsSSA)
>      RegInfo.leaveSSA();
>    assert(RegInfo.tracksLiveness());
>    if (!YamlMF.TracksRegLiveness)
>      RegInfo.invalidateLiveness();
>    RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
> +
> +  // Parse the virtual register information.
> +  for (const auto &VReg : YamlMF.VirtualRegisters) {
> +    const auto *RC = getRegClass(MF, VReg.Class.Value);
> +    if (!RC)
> +      return error(VReg.Class.SourceRange.Start,
> +                   Twine("use of undefined register class '") +
> +                       VReg.Class.Value + "'");
> +    // TODO: create the mapping from IDs to registers so that the virtual
> +    // register references can be parsed corretly.

s/corretly/correctly/

I'm not following this TODO.  How is that different from the mapping
used in `getRegClass()`?

> +    RegInfo.createVirtualRegister(RC);
> +  }
>    return false;
>  }
>  
> @@ -392,6 +416,26 @@
>                        Error.getFixIts());
>  }
>  
> +void MIRParserImpl::initNames2RegClasses(const MachineFunction &MF) {
> +  if (!Names2RegClasses.empty())
> +    return;
> +  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
> +  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) {
> +    const auto *RC = TRI->getRegClass(I);
> +    Names2RegClasses.insert(
> +        std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));
> +  }
> +}
> +
> +const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,
> +                                                      StringRef Name) {
> +  initNames2RegClasses(MF);
> +  auto RegClassInfo = Names2RegClasses.find(Name);
> +  if (RegClassInfo == Names2RegClasses.end())
> +    return nullptr;
> +  return RegClassInfo->getValue();
> +}
> +
>  MIRParser::MIRParser(std::unique_ptr<MIRParserImpl> Impl)
>      : Impl(std::move(Impl)) {}
>