[PATCH] D11055: [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2 operand

[scott douglass]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL241800: [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2 (authored by scott-0).

Changed prior to commit:
  http://reviews.llvm.org/D11055?vs=29309&id=29327#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D11055

Files:
  llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll

Index: llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll
===================================================================
--- llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll
+++ llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll
@@ -65,6 +65,10 @@
 
     ADD      r3, r3, r1          // T2
 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
+    ADD      r4, r4, pc          // T2
+// CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
+    ADD      pc, pc, r2          // T2
+// CHECK: add  pc, r2               @ encoding: [0x97,0x44]
 
 // ADD (SP plus immediate) A8.8.9
     ADD      sp, sp, #20         // T2
Index: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5467,22 +5467,32 @@
     CanAcceptPredicationCode = true;
 }
 
-// \brief Some Thumb1 instructions have two operand forms that are not
+// \brief Some Thumb instructions have two operand forms that are not
 // available as three operand, convert to two operand form if possible.
 //
 // FIXME: We would really like to be able to tablegen'erate this.
 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
                                                  bool CarrySetting,
                                                  OperandVector &Operands) {
-  if (Operands.size() != 6 || !isThumbOne())
+  if (Operands.size() != 6)
     return;
 
   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
   ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
   if (!Op3.isReg() || !Op4.isReg())
     return;
 
+  // For most Thumb2 cases we just generate the 3 operand form and reduce
+  // it in processInstruction(), but for ADD involving PC the the 3 operand
+  // form won't accept PC so we do the transformation here.
   ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
+  if (isThumbTwo()) {
+    if (Mnemonic != "add" ||
+        !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
+          (Op5.isReg() && Op5.getReg() == ARM::PC)))
+      return;
+  } else if (!isThumbOne())
+    return;
 
   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D11055.29327.patch
Type: text/x-patch
Size: 2341 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150709/4f8035be/attachment.bin>