[llvm] r241800 - [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2

[Scott Douglass]

Author: scott-0
Date: Thu Jul  9 09:13:41 2015
New Revision: 241800

URL: http://llvm.org/viewvc/llvm-project?rev=241800&view=rev
Log:
[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2

Differential Revision: http://reviews.llvm.org/D11055

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=241800&r1=241799&r2=241800&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul  9 09:13:41 2015
@@ -5467,14 +5467,14 @@ void ARMAsmParser::getMnemonicAcceptInfo
     CanAcceptPredicationCode = true;
 }
 
-// \brief Some Thumb1 instructions have two operand forms that are not
+// \brief Some Thumb instructions have two operand forms that are not
 // available as three operand, convert to two operand form if possible.
 //
 // FIXME: We would really like to be able to tablegen'erate this.
 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
                                                  bool CarrySetting,
                                                  OperandVector &Operands) {
-  if (Operands.size() != 6 || !isThumbOne())
+  if (Operands.size() != 6)
     return;
 
   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
@@ -5482,7 +5482,17 @@ void ARMAsmParser::tryConvertingToTwoOpe
   if (!Op3.isReg() || !Op4.isReg())
     return;
 
+  // For most Thumb2 cases we just generate the 3 operand form and reduce
+  // it in processInstruction(), but for ADD involving PC the the 3 operand
+  // form won't accept PC so we do the transformation here.
   ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
+  if (isThumbTwo()) {
+    if (Mnemonic != "add" ||
+        !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
+          (Op5.isReg() && Op5.getReg() == ARM::PC)))
+      return;
+  } else if (!isThumbOne())
+    return;
 
   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||

Modified: llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll?rev=241800&r1=241799&r2=241800&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll (original)
+++ llvm/trunk/test/MC/ARM/thumb2-narrow-dp.ll Thu Jul  9 09:13:41 2015
@@ -65,6 +65,10 @@
 
     ADD      r3, r3, r1          // T2
 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
+    ADD      r4, r4, pc          // T2
+// CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
+    ADD      pc, pc, r2          // T2
+// CHECK: add  pc, r2               @ encoding: [0x97,0x44]
 
 // ADD (SP plus immediate) A8.8.9
     ADD      sp, sp, #20         // T2