[llvm] r241790 - Fix shift legalization and lowering for big constants.
Pawel Bylica
chfast at gmail.com
Thu Jul 9 01:01:36 PDT 2015
Author: chfast
Date: Thu Jul 9 03:01:36 2015
New Revision: 241790
URL: http://llvm.org/viewvc/llvm-project?rev=241790&view=rev
Log:
Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.
Reviewers: nadav, majnemer, sanjoy, RKSimon
Subscribers: RKSimon, llvm-commits
Differential Revision: http://reviews.llvm.org/D10767
Added:
llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=241790&r1=241789&r2=241790&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Jul 9 03:01:36 2015
@@ -1358,9 +1358,9 @@ std::pair <SDValue, SDValue> DAGTypeLega
return ExpandChainLibCall(LC, Node, false);
}
-/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
+/// N is a shift by a value that needs to be expanded,
/// and the shift amount is a constant 'Amt'. Expand the operation.
-void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
+void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
SDValue &Lo, SDValue &Hi) {
SDLoc DL(N);
// Expand the incoming operand to be shifted, so that we have its parts
@@ -1381,12 +1381,12 @@ void DAGTypeLegalizer::ExpandShiftByCons
EVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
- if (Amt > VTBits) {
+ if (Amt.ugt(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
- } else if (Amt > NVTBits) {
+ } else if (Amt.ugt(NVTBits)) {
Lo = DAG.getConstant(0, DL, NVT);
Hi = DAG.getNode(ISD::SHL, DL,
- NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
+ NVT, InL, DAG.getConstant(-Amt + NVTBits, DL, ShTy));
} else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, DL, NVT);
Hi = InL;
@@ -1405,16 +1405,15 @@ void DAGTypeLegalizer::ExpandShiftByCons
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SRL, DL, NVT, InL,
- DAG.getConstant(NVTBits - Amt, DL, ShTy)));
+ DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
}
return;
}
if (N->getOpcode() == ISD::SRL) {
- if (Amt > VTBits) {
- Lo = DAG.getConstant(0, DL, NVT);
- Hi = DAG.getConstant(0, DL, NVT);
- } else if (Amt > NVTBits) {
+ if (Amt.ugt(VTBits)) {
+ Lo = Hi = DAG.getConstant(0, DL, NVT);
+ } else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRL, DL,
NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
Hi = DAG.getConstant(0, DL, NVT);
@@ -1426,19 +1425,19 @@ void DAGTypeLegalizer::ExpandShiftByCons
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
- DAG.getConstant(NVTBits - Amt, DL, ShTy)));
+ DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
}
return;
}
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
- if (Amt > VTBits) {
+ if (Amt.ugt(VTBits)) {
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
- } else if (Amt > NVTBits) {
+ } else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
- DAG.getConstant(Amt-NVTBits, DL, ShTy));
+ DAG.getConstant(Amt - NVTBits, DL, ShTy));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
} else if (Amt == NVTBits) {
@@ -1450,7 +1449,7 @@ void DAGTypeLegalizer::ExpandShiftByCons
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
- DAG.getConstant(NVTBits - Amt, DL, ShTy)));
+ DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
}
}
@@ -2178,7 +2177,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shif
// If we can emit an efficient shift operation, do so now. Check to see if
// the RHS is a constant.
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
- return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
+ return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
// If we can determine that the high bit of the shift is zero or one, even if
// the low bits are variable, emit this shift in an optimized form.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=241790&r1=241789&r2=241790&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Jul 9 03:01:36 2015
@@ -167,7 +167,7 @@ private:
SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index);
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
-
+
std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
SDNode *Node, bool isSigned);
std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
@@ -347,7 +347,7 @@ private:
void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
- void ExpandShiftByConstant(SDNode *N, unsigned Amt,
+ void ExpandShiftByConstant(SDNode *N, const APInt &Amt,
SDValue &Lo, SDValue &Hi);
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=241790&r1=241789&r2=241790&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 9 03:01:36 2015
@@ -23167,7 +23167,7 @@ static SDValue PerformSHLCombine(SDNode
// We shift all of the values by one. In many cases we do not have
// hardware support for this operation. This is better expressed as an ADD
// of two values.
- if (N1SplatC->getZExtValue() == 1)
+ if (N1SplatC->getAPIntValue() == 1)
return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
}
Added: llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll?rev=241790&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll (added)
+++ llvm/trunk/test/CodeGen/X86/legalize-shl-vec.ll Thu Jul 9 03:01:36 2015
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+define <2 x i256> @test_shl(<2 x i256> %In) {
+ %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+ %Out = shl <2 x i256> %In, %Amt
+ ret <2 x i256> %Out
+
+ ; CHECK-LABEL: test_shl
+ ; CHECK: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK: retq
+}
+
+define <2 x i256> @test_srl(<2 x i256> %In) {
+ %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+ %Out = lshr <2 x i256> %In, %Amt
+ ret <2 x i256> %Out
+
+ ; CHECK-LABEL: test_srl
+ ; CHECK: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK-NEXT: movq $0
+ ; CHECK: retq
+}
+
+define <2 x i256> @test_sra(<2 x i256> %In) {
+ %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+ %Out = ashr <2 x i256> %In, %Amt
+ ret <2 x i256> %Out
+
+ ; CHECK-LABEL: test_sra
+ ; CHECK: sarq $63
+}
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