[llvm] AMDGPU: Add helper function for implicit parameter offsets.

[Matt Arsenault]

> On Jul 8, 2015, at 10:06 AM, Zoltan Gilian <zoltan.gilian at gmail.com> wrote:
> 
> ---
> lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 12 ++++++++++++
> lib/Target/AMDGPU/AMDGPUISelLowering.h   |  7 +++++++
> lib/Target/AMDGPU/R600ISelLowering.cpp   |  6 ++++--
> lib/Target/AMDGPU/SIISelLowering.cpp     |  4 ++--
> 4 files changed, 25 insertions(+), 4 deletions(-)

LGTM with some trivial changes.


> 
> diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> index 9479d23..1c8d9cd 100644
> --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> @@ -2645,6 +2645,18 @@ SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
>   return DAG.getRegister(VirtualRegister, VT);
> }
> 
> +unsigned AMDGPUTargetLowering::GetImplicitParameterOffset(

Function name should start with lowercase letter. I would also prefer this return uint32_t

> +    const AMDGPUMachineFunction *MFI, const ImplicitParameter param) const {
param should be capitalized

> +  uint64_t ArgOffset = MFI->ABIArgOffset;
> +  switch (param) {
> +  case GRID_DIM:
> +    return ArgOffset;
> +  case GRID_OFFSET:
> +    return ArgOffset + 4;
> +  }
> +  llvm_unreachable("unexpected implicit parameter type");
> +}
> +
> #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
> 
> const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
> diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.h b/lib/Target/AMDGPU/AMDGPUISelLowering.h
> index fbb7d3c..c87b2bd 100644
> --- a/lib/Target/AMDGPU/AMDGPUISelLowering.h
> +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.h
> @@ -207,6 +207,13 @@ public:
>   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
>                                        const TargetRegisterClass *RC,
>                                        unsigned Reg, EVT VT) const;
> +
> +  enum ImplicitParameter { GRID_DIM, GRID_OFFSET };
Can you break these onto separate lines?

> +
> +  /// \brief Helper function that returns the byte offset of the given
> +  /// type of implicit parameter.
> +  unsigned GetImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
> +                                      const ImplicitParameter param) const;
> };
> 
> namespace AMDGPUISD {
> diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
> index 8357b6d..828d60f 100644
> --- a/lib/Target/AMDGPU/R600ISelLowering.cpp
> +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
> @@ -815,8 +815,10 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
>     case Intrinsic::r600_read_local_size_z:
>       return LowerImplicitParameter(DAG, VT, DL, 8);
> 
> -    case Intrinsic::AMDGPU_read_workdim:
> -      return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4);
> +    case Intrinsic::AMDGPU_read_workdim: {
> +      auto ByteOffset = GetImplicitParameterOffset(MFI, GRID_DIM);
Don’t use auto here

> +      return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4);
> +    }
> 
>     case Intrinsic::r600_read_tgid_x:
>       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
> index 32f452e..9940f6f 100644
> --- a/lib/Target/AMDGPU/SIISelLowering.cpp
> +++ b/lib/Target/AMDGPU/SIISelLowering.cpp
> @@ -926,6 +926,7 @@ SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
> SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
>                                                   SelectionDAG &DAG) const {
>   MachineFunction &MF = DAG.getMachineFunction();
> +  auto MFI = MF.getInfo<SIMachineFunctionInfo>();
>   const SIRegisterInfo *TRI =
>       static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
> 
> @@ -964,8 +965,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
> 
>   case Intrinsic::AMDGPU_read_workdim:
>     return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> -                          MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
> -                          false);
> +                          GetImplicitParameterOffset(MFI, GRID_DIM), false);
> 
>   case Intrinsic::r600_read_tgid_x:
>     return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
> -- 
> 2.4.2

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