[PATCH] D9107: Fix CombineToPostIndexedLoadStore in DAGCombiner.cpp

[Quentin Colombet]

Hi François,

Thanks for fixing the tests.
I’ll have a quick look at the tests that you’ve XFAILed before deciding whether or not this is OK.

Cheers,
-Quentin


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Comment at: test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll:29
@@ -28,1 +28,3 @@
+; CHECK:      ldr     r1, [r0], #4
+; CHECK:      ldr     r2, [r0]
   call void @t(i32 0, %struct.s* @v);
----------------
Looks like the load store optimizer could use some improvement to catch this case (assuming r0 is not used afterward).

================
Comment at: test/CodeGen/ARM/avoid-cpsr-rmw.ll:31
@@ -30,3 +30,2 @@
-; CHECK-NOT: muls
   %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
   %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
----------------
Could you comment why this check is failing now?
I am not saying this is wrong, I’d like to check we are not missing something.


http://reviews.llvm.org/D9107