[llvm] r241600 - [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595

[Krzysztof Parzyszek]

Author: kparzysz
Date: Tue Jul  7 11:02:11 2015
New Revision: 241600

URL: http://llvm.org/viewvc/llvm-project?rev=241600&view=rev
Log:
[Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595


Modified:
    llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp

Modified: llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/BitTracker.cpp?rev=241600&r1=241599&r2=241600&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/BitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/BitTracker.cpp Tue Jul  7 11:02:11 2015
@@ -527,8 +527,7 @@ BT::RegisterCell BT::MachineEvaluator::e
 
 BT::RegisterCell BT::MachineEvaluator::eASL(const RegisterCell &A1,
       uint16_t Sh) const {
-  uint16_t W = A1.width();
-  assert(Sh <= W);
+  assert(Sh <= A1.width());
   RegisterCell Res = RegisterCell::ref(A1);
   Res.rol(Sh);
   Res.fill(0, Sh, BitValue::Zero);
@@ -644,8 +643,7 @@ BT::RegisterCell BT::MachineEvaluator::e
 
 BT::RegisterCell BT::MachineEvaluator::eSET(const RegisterCell &A1,
       uint16_t BitN) const {
-  uint16_t W = A1.width();
-  assert(BitN < W);
+  assert(BitN < A1.width());
   RegisterCell Res = RegisterCell::ref(A1);
   Res[BitN] = BitValue::One;
   return Res;
@@ -654,8 +652,7 @@ BT::RegisterCell BT::MachineEvaluator::e
 
 BT::RegisterCell BT::MachineEvaluator::eCLR(const RegisterCell &A1,
       uint16_t BitN) const {
-  uint16_t W = A1.width();
-  assert(BitN < W);
+  assert(BitN < A1.width());
   RegisterCell Res = RegisterCell::ref(A1);
   Res[BitN] = BitValue::Zero;
   return Res;
@@ -722,6 +719,7 @@ BT::RegisterCell BT::MachineEvaluator::e
 BT::RegisterCell BT::MachineEvaluator::eINS(const RegisterCell &A1,
       const RegisterCell &A2, uint16_t AtN) const {
   uint16_t W1 = A1.width(), W2 = A2.width();
+  (void)W1;
   assert(AtN < W1 && AtN+W2 <= W1);
   // Copy bits from A1, insert A2 at position AtN.
   RegisterCell Res = RegisterCell::ref(A1);
@@ -1017,6 +1015,7 @@ void BT::subst(RegisterRef OldRR, Regist
   BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);
   uint16_t OMB = OM.first(), OME = OM.last();
   uint16_t NMB = NM.first(), NME = NM.last();
+  (void)NME;
   assert((OME-OMB == NME-NMB) &&
          "Substituting registers of different lengths");
   for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) {

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=241600&r1=241599&r2=241600&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Tue Jul  7 11:02:11 2015
@@ -195,15 +195,13 @@ bool HexagonEvaluator::evaluate(const Ma
       return eIMM(Op.getImm(), W);
     if (!Op.isReg())
       return RegisterCell::self(0, W);
-    uint16_t w = getRegBitWidth(Reg[N]);
-    assert(w == W && "Register width mismatch");
+    assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
     return rc(N);
   };
   // Extract RW low bits of the cell.
   auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
         -> BT::RegisterCell {
-    uint16_t W = RC.width();
-    assert(RW <= W);
+    assert(RW <= RC.width());
     return eXTR(RC, 0, RW);
   };
   // Extract RW high bits of the cell.
@@ -216,8 +214,7 @@ bool HexagonEvaluator::evaluate(const Ma
   // Extract N-th halfword (counting from the least significant position).
   auto half = [this] (const BT::RegisterCell &RC, unsigned N)
         -> BT::RegisterCell {
-    uint16_t W = RC.width();
-    assert(N*16+16 <= W);
+    assert(N*16+16 <= RC.width());
     return eXTR(RC, N*16, N*16+16);
   };
   // Shuffle bits (pick even/odd from cells and merge into result).