[PATCH] D9645: [X86][SSE] Vectorized i64 uniform constant SRA shifts

[Simon Pilgrim]

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Comment at: test/CodeGen/X86/vector-shift-ashr-128.ll:988
@@ -990,3 +987,3 @@
   ret <2 x i64> %shift
 }
 
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delena wrote:
> Hi Simon,
> 
> I think that the result here will be incorrect. Let's take a positive 64-bit number (2^34)-1. After the arithmetic shift-right-7 you should receive
> (2^27)-1. But "vpsrad" will take the source as negative 32-bit and you'll see (2^32)-1 in %xmm1 and the correct result will be after "vpsrlq"  in %xmm0.
> 
> Upper = (2^32)-1
> Lower = (2^27)-1
> Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3}); <= the result is incorrect
Hi Elena, taking your example (as a v1i64 for simplicity):

in: 00000003ffffffff (ffffffff 00000003) as v2i32
upper: ashr32 (in, 7): 00000000ffffffff (ffffffff 00000000) 2nd 32-bit lane used 
lower: lshr64(in, 7): 0000000007ffffff (07ffffff 00000000) 1st 32-bit lane used
shuffle32(ashr32, lshr64, 4,1,3,2): 0000000007ffffff (07ffffff 00000000)

Which I believe is correct, no?


Repository:
  rL LLVM

http://reviews.llvm.org/D9645