[PATCH] WebAssembly: start instructions

Dan Gohman dan433584 at gmail.com
Wed Jul 1 14:38:02 PDT 2015


================
Comment at: lib/Target/WebAssembly/WebAssembly.td:26
@@ +25,3 @@
+def FeatureAddr64 : SubtargetFeature<"addr64", "HasAddr64", "false",
+                                     "Enable 64-bit address space">;
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
----------------
Ok.

================
Comment at: lib/Target/WebAssembly/WebAssembly.td:30
@@ -27,1 +29,3 @@
+def FeatureThreads : SubtargetFeature<"threads", "HasThreads", "false",
+                                      "Enable threads and atomics">;
 
----------------
Ok.

================
Comment at: lib/Target/WebAssembly/WebAssembly.td:61
@@ -51,1 +60,3 @@
+def : ProcessorModel<"bleeding-edge-64", NoSchedModel,
+                     [FeatureAddr64, FeatureSIMD128, FeatureThreads]>;
 
----------------
The way similar things work on other targets is that there's one ProcessorModel which supports both 32-bit and 64-bit mode.

================
Comment at: lib/Target/WebAssembly/WebAssemblyInstrAtomics.td:15
@@ +14,3 @@
+// TODO: Implement atomic instructions.
+// Note: use Requires<[HasThreads]>, fall back to regular load/store otherwise.
+
----------------
FWIW, see
https://github.com/llvm-mirror/llvm/blob/5be64c403b49bb0d6a2b528613e813d04108b6c3/lib/Target/ARM/ARMTargetMachine.cpp#L321
for how something similar is done on ARM.

================
Comment at: lib/Target/WebAssembly/WebAssemblyInstrInfo.td:19
@@ +18,3 @@
+def HasAddr64 : Predicate<"Subtarget->hasAddr64()">,
+                          AssemblerPredicate<"FeatureAddr64", "addr64">;
+def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
----------------
We should add a HasAddr32 predicate too, since 64-bit mode can't use 32-bit addresses.

================
Comment at: lib/Target/WebAssembly/WebAssemblySubtarget.h:32
@@ -31,2 +31,3 @@
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
-  bool HasSIMD;
+  bool HasAddr64;
+  bool HasSIMD128;
----------------
64-bit mode is implied by TargetTriple.isArch64Bit() so we don't need a separate field here.

http://reviews.llvm.org/D10880

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/






More information about the llvm-commits mailing list