[PATCH] [mips] MFC0, MTC0 changes, COP0 register class definition.

[Daniel Sanders]

In the commit, I've fixed a couple issues that came up when running 'ninja check'.

- Some little endian disassembler tests failed because they had the same opcode as big endian. I've byte-swapped them.
- Two disassembler tests failed because their expectation was different for the same opcode as the other ISA's.

I also marked DMFC0 as being part of MIPS3 like the other DM[FT]C0's.


http://reviews.llvm.org/D10567

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