[PATCH] [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics.

[Michael Zolotukhin]

Hi Hao,

Thanks for the explanation!

The code looks good to me now. I'd also recommend to check-in shared part and the target implementations in separate commits - by the logic everything should work fine even without them, right? (and that's what will happen on other targets)

Best regards,
Michael


================
Comment at: test/CodeGen/AArch64/aarch64-interleaved-accesses.ll:13-15
@@ +12,5 @@
+
+; CHECK-LABEL: load_delat3:
+; CHECK: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
+define <4 x i32> @load_delat3(i32* %ptr) {
+  %base = bitcast i32* %ptr to <12 x i32>*
----------------
s/delat/delta/

================
Comment at: test/CodeGen/ARM/arm-interleaved-accesses.ll:13-15
@@ +12,5 @@
+
+; CHECK-LABEL: load_delat3:
+; CHECK: vld3.32 {d16, d17, d18}, [r0]
+define <2 x i32> @load_delat3(i32* %ptr) {
+  %base = bitcast i32* %ptr to <6 x i32>*
----------------
s/delat/delta/ ?

http://reviews.llvm.org/D10533

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