[PATCH] AArch64: Add aditional Cyclone macroop fusion opportunities

[Matthias Braun]

Hi t.p.northover,

Related to rdar://19205407

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10746

Files:
  lib/Target/AArch64/AArch64InstrInfo.cpp

Index: lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.cpp
+++ lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1455,23 +1455,41 @@
 
 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
                                               MachineInstr *Second) const {
-  // Cyclone can fuse CMN, CMP followed by Bcc.
-
-  // FIXME: B0 can also fuse:
-  // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
-  if (Second->getOpcode() != AArch64::Bcc)
-    return false;
-  switch (First->getOpcode()) {
-  default:
-    return false;
-  case AArch64::SUBSWri:
-  case AArch64::ADDSWri:
-  case AArch64::ANDSWri:
-  case AArch64::SUBSXri:
-  case AArch64::ADDSXri:
-  case AArch64::ANDSXri:
-    return true;
+  // Cyclone can fuse CMN, CMP, TST followed by Bcc.
+  unsigned SecondOpcode = Second->getOpcode();
+  if (SecondOpcode == AArch64::Bcc) {
+    switch (First->getOpcode()) {
+    default:
+      return false;
+    case AArch64::SUBSWri:
+    case AArch64::ADDSWri:
+    case AArch64::ANDSWri:
+    case AArch64::SUBSXri:
+    case AArch64::ADDSXri:
+    case AArch64::ANDSXri:
+      return true;
+    }
+  }
+  // Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
+  if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
+      SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
+    switch (First->getOpcode()) {
+    default:
+      return false;
+    case AArch64::ADDWri:
+    case AArch64::ADDXri:
+    case AArch64::ANDWri:
+    case AArch64::ANDXri:
+    case AArch64::EORWri:
+    case AArch64::EORXri:
+    case AArch64::ORRWri:
+    case AArch64::ORRXri:
+    case AArch64::SUBWri:
+    case AArch64::SUBXri:
+      return true;
+    }
   }
+  return false;
 }
 
 MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(

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