[PATCH] AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
Matt Arsenault
arsenm2 at gmail.com
Thu Jun 25 10:48:12 PDT 2015
> On Jun 25, 2015, at 4:08 AM, Marek Olšák <maraeo at gmail.com> wrote:
>
> +define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
> +main_body:
> + %22 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0
> + %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0
> + %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0)
> + %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4)
> + %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8)
> + %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12)
> + %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16)
> + %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20)
> + %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 24)
> + %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 28)
> + %32 = bitcast [34 x <8 x i32>] addrspace(2)* %3 to <32 x i8> addrspace(2)*
> + %33 = load <32 x i8>, <32 x i8> addrspace(2)* %32, align 32, !tbaa !0
> + %34 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
> + %35 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
> + %36 = fptosi float %34 to i32
> + %37 = fptosi float %35 to i32
> + %38 = ashr i32 %36, 3
> + %39 = insertelement <4 x i32> undef, i32 %38, i32 0
> + %40 = insertelement <4 x i32> %39, i32 %37, i32 1
> + %41 = insertelement <4 x i32> %40, i32 0, i32 2
> + %42 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> %41, <32 x i8> %33, i32 2)
> + %43 = extractelement <4 x i32> %42, i32 0
> + %44 = and i32 %36, 7
> + %45 = shl i32 1, %44
> + %46 = and i32 %43, %45
> + %47 = icmp eq i32 %46, 0
> + %. = select i1 %47, float %28, float %24
> + %.8 = select i1 %47, float %29, float %25
> + %.9 = select i1 %47, float %30, float %26
> + %.10 = select i1 %47, float %31, float %27
> + %48 = call i32 @llvm.SI.packf16(float %., float %.8)
> + %49 = bitcast i32 %48 to float
> + %50 = call i32 @llvm.SI.packf16(float %.9, float %.10)
> + %51 = bitcast i32 %50 to float
> + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
> + ret void
> +}
> +
> +declare float @llvm.SI.load.const(<16 x i8>, i32) #1
> +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
> +declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1
> +declare i32 @llvm.SI.packf16(float, float) #1
> +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
> +
> +attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
> +attributes #1 = { nounwind readnone }
> +
> +!0 = !{!"const", null, i32 1}
Can you simplify this testcase?
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