[PATCH] [mips] [IAS] Add partial support for the ULW pseudo-instruction.

[Daniel Sanders]

> expandUlw() looks very similar to expandUlh(). Could we share code between them?


That's not nearly as similar as I thought it was. I thought it was >90% similar with just the odd line or two different but it is actually ~90% different with the odd similar chunk. Sorry to mess you about but could you roll back to the separated version in the previous diff?


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:2389-2394
@@ +2388,8 @@
+
+    // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
+    // because it will make our output more similar to GAS'.
+    // NOTE: If there is no source register specified in the ULW, the parser
+    // will interpret it as $0.
+    if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
+      createAddu(ATReg, ATReg, SrcReg, Instructions);
+  }
----------------
tomatabacu wrote:
> dsanders wrote:
> > Could you tell me the cases where this matters? loadImmediate() will usually emit the same thing here.
> For example:
>   ulw/ulhu $8, 0x8000($9)
> 
> If we give the SrcReg to loadImmediate, we generate:
>   ori   $1, $9, 32768
> 
> If we do the addd locally, we generate:
>   ori   $1, $zero, 32768
>   addu  $1, $1, $9
> 
> GAS generates:
>   addiu $1, $zero, 32768
>   addu  $1, $1, $9
> 
> I added a code comment with this example to D9671.
Thanks. One thing to point out. This:
  ori   $1, $zero, 32768
  addu  $1, $1, $9
is not equivalent to:
  addiu $1, $zero, 32768
  addu  $1, $1, $9
because addiu uses a simm16 (giving 0xffff8000) and ori uses a uimm16 (giving 0x00008000). I suspect we have a bug in loadImmediate(). GAS probably shouldn't silently change 32768 to -32768 either though.

================
Comment at: test/MC/Mips/mips-expansions-bad.s:40
@@ +39,3 @@
+
+ .set mips32r6
+  ulw $5, 0
----------------
Nit: Indentation, likewise for the other .set's

http://reviews.llvm.org/D9663

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