[PATCH] MIR Serialization: Serialize the implicit register flags.

[Alex Lorenz]

Hi dexonsmith, bob.wilson, bogner,

This patch is based on a previous serialization patch that serializes register mask machine operands (http://reviews.llvm.org/D10673).

This patch serializes the implicit register flag. This patch introduces two new keywords into the
machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit
register operands, and the 'implicit-def' keyword is used for the register operands that have the 
implicit and define flag. Examples:

      CMP32ri8 %edi, 10, implicit-def %eflags
      JG_1 %bb.2.exit, implicit %eflags

This patch also adds a way to control the implicit machine operands - if a parser encounters a
register operand with an 'implicit' or 'implicit-def' flag, it will assume that this instruction specifies
all the implicit operands explicitly. But if the parser encounters an instruction that has no implicit register
operands, it will add the implicit register operands that are specified by the instruction information. 
This means that the instruction:

      CMP32ri8 %edi, 10

Is equivalent to:

      CMP32ri8 %edi, 10, implicit-def %eflags

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10709

Files:
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  test/CodeGen/MIR/X86/expected-register-after-flags.mir
  test/CodeGen/MIR/X86/implicit-register-flag.mir
  test/CodeGen/MIR/X86/machine-instructions.mir
  test/CodeGen/MIR/X86/register-mask-operands.mir

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/
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