[llvm] r240291 - Fix shl folding in DAG combiner.

[Pawel Bylica]

Author: chfast
Date: Mon Jun 22 10:58:11 2015
New Revision: 240291

URL: http://llvm.org/viewvc/llvm-project?rev=240291&view=rev
Log:
Fix shl folding in DAG combiner.

Summary: The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared.

Test Plan: A regression test included.

Reviewers: andreadb

Reviewed By: andreadb

Subscribers: andreadb, test, llvm-commits

Differential Revision: http://reviews.llvm.org/D10602

Added:
    llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=240291&r1=240290&r2=240291&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 22 10:58:11 2015
@@ -4275,7 +4275,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
   if (isNullConstant(N0))
     return N0;
   // fold (shl x, c >= size(x)) -> undef
-  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
+  if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
     return DAG.getUNDEF(VT);
   // fold (shl x, 0) -> x
   if (N1C && N1C->isNullValue())

Added: llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll?rev=240291&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll Mon Jun 22 10:58:11 2015
@@ -0,0 +1,8 @@
+; RUN: llc < %s | FileCheck %s
+
+;CHECK-LABEL: test
+define <2 x i256> @test() {
+  %S = shufflevector <2 x i256> zeroinitializer, <2 x i256> <i256 -1, i256 -1>, <2 x i32> <i32 0, i32 2>
+  %B = shl <2 x i256> %S, <i256 -1, i256 -1> ; DAG Combiner crashes here
+  ret <2 x i256> %B
+}