[PATCH] [mips] MFC0, MTC0 changes, COP0 register class definition.

[Simon Dardis]

Hi dsanders,

MFC0 and MTC0 were incorrectly defined as taking a pair of GP32Rs and immediate, when they take a GP32R, COP0[1] and an immediate.

[1] New register class corresponding to the registers of co-processor 0.

http://reviews.llvm.org/D10567

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td
  lib/Target/Mips/MipsOptionRecord.h
  lib/Target/Mips/MipsRegisterInfo.td

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