[PATCH]Avoid redundant select node in early if conversation pass

[yi_jiang]

Thank you! In r240072.
> On Jun 18, 2015, at 3:30 PM, Quentin Colombet <qcolombet at apple.com> wrote:
> 
> LGTM.
> 
> Thanks Yi!
> 
> Q.
>> On Jun 18, 2015, at 3:26 PM, yi_jiang <yjiang at apple.com <mailto:yjiang at apple.com>> wrote:
>> 
>> Hi Quentin, 
>> 
>> Thank you for your comments! I made some adjustments on the new patch.  For the message in the == case, I tried a few settings while found that printing nothing looks like the best since the new PHI node will be printed right way. Here is the example:
>> 
>> If-converting %vreg1<def> = PHI %vreg0, <BB#0>, %vreg3, <BB#4>, %vreg3, <BB#3>; GPR32common:%vreg1 GPR32all:%vreg0,%vreg3,%vreg3
>>           --> %vreg1<def> = PHI %vreg0, <BB#0>, %vreg3, <BB#2>; GPR32common:%vreg1 GPR32all:%vreg0,%vreg3
>> If-converting %vreg2<def> = PHI %vreg8, <BB#0>, %vreg5, <BB#4>, %vreg4, <BB#3>; GPR32common:%vreg2,%vreg8 GPR32all:%vreg5,%vreg4
>>           --> %vreg18<def> = CSINCWr %vreg5, %vreg2, 10, %NZCV<imp-use>; GPR32common:%vreg18,%vreg2 GPR32:%vreg5
>>           --> %vreg2<def> = PHI %vreg8, <BB#0>, %vreg18, <BB#2>; GPR32common:%vreg2,%vreg8,%vreg18
>> <ifcvt2.patch>
>>           --> %vreg2<def> = PHI %vreg8, <BB#0>, %vreg18, <BB#2>; GPR32common:%vreg2,%vreg8,%vreg18
>> 
>>> On Jun 18, 2015, at 1:29 PM, Quentin Colombet <qcolombet at apple.com <http://apple.com/>> wrote:
>>> 
>>> Hi Yi,
>>> 
>>> The patch looks good to me with a few nitpicks. Nice catch!
>>> 
>>> A couple of nitpicks:
>>> 1.
>>> +    if (PI.TReg == PI.FReg) {
>>> +      DstReg = PI.TReg;
>>> +    } else {
>>> +      DEBUG(dbgs() << "If-converting " << *PI.PHI);
>>> 
>>> Please move this DEBUG output before the if, and print a message in the == case.
>>> 
>>> 2.
>>> Although this is obvious what you are doing, I would like a comment saying that we do not need the select when both sources are equal.
>>> 
>>> Thanks,
>>> -Quentin
>>> 
>>> 
>>>> On Jun 18, 2015, at 12:34 PM, yi_jiang <yjiang at apple.com <mailto:yjiang at apple.com>> wrote:
>>>> 
>>>> Hi, 
>>>> 
>>>> We found that early if-conversion pass may introduce some redundant select node. Please see the example below, I use llvm IR here just to make it a little easier to read although early if-conversion is dealing machine instructions.  When we if-convert a diamond below, If the tail basic block(while.body) has extra predecessors(while.body.lr.ph), we need to insert select in the head basic block(while.cond) and rewrite the PHI in the tail basic block(while.body). However, if this select node is actually selecting same value, that is redundant. In our case, it is the %j.012 with incoming value of %inc from both %if.then and %if.else. And since early if conversation is pretty late in codegen so the latter passes won’t be able to remove this redundancy. This patch is to remove this redundancy. Bzip2 decompression will benefit from this patch. 
>>>> 
>>>> while.cond:  ; Head BB
>>>>   ...
>>>>   br i1 %cmp2, label %if.then, label %if.else
>>>> 
>>>> if.then:   ;TBB
>>>>   %inc2 = add nsw i32 %i.011, 1
>>>>   br label %while.body
>>>> 
>>>> if.else:   ;FBB
>>>>   %dec = add nsw i32 %i.011, -1
>>>>   br label %while.body
>>>> 
>>>> while.body:   ;Tail BB
>>>>   %j.012 = phi i32 [ %sub, %while.body.lr.ph ], [ %inc, %if.then ], [ %inc, %if.else ]   ;we dont need a select of %inc and %inc from the TBB/FBB in Head BB
>>>>   %i.011 = phi i32 [ %a, %while.body.lr.ph ], [ %inc2, %if.then ], [ %dec, %if.else ]    ;we DO need a select of %inc2 and %dec from the TBB/FBB in Head BB
>>>>   ...
>>>>   br i1 %cmp1, label %while.end, label %while.cond
>>>> 
>>>> 
>>>> <ifcvt.patch>
>>>> 
>>>> 
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