[PATCH] [TableGen] Add alternative register matching support to AsmMatcher
Dylan McKay
dylanmckay34 at gmail.com
Wed Jun 17 03:28:53 PDT 2015
Note that the AArch64 example is a bad one, because there are several
different registers such have the same alternative names (it is not a
one-to-one mapping) and so TableGen would crash in this case.
On Jun 17, 2015 2:47 PM, "Dylan McKay" <dylanmckay34 at gmail.com> wrote:
> The machinery is in place, but AsmMatcher support isn’t implemented (I
> couldn’t see any mention of it in utils/TableGen/AsmMatcherEmitter.cpp.
> The instruction printer tablegen backend supports it (through the use of
> the PRINT_ALIAS_INSTR preprocessor define.
>
> AArch64 uses the alternative name feature. Here is its AsmParser.cpp:
>
> static unsigned matchVectorRegName(StringRef Name) {
> return StringSwitch<unsigned>(Name.lower())
> .Case("v0", AArch64::Q0)
> .Case("v1", AArch64::Q1)
> .Case("v2", AArch64::Q2)
> .Case("v3", AArch64::Q3)
> .Case("v4", AArch64::Q4)
> .Case("v5", AArch64::Q5)
> .Case("v6", AArch64::Q6)
> .Case("v7", AArch64::Q7)
> .Case("v8", AArch64::Q8)
> .Case("v9", AArch64::Q9)
> .Case("v10", AArch64::Q10)
> .Case("v11", AArch64::Q11)
> .Case("v12", AArch64::Q12)
> .Case("v13", AArch64::Q13)
> .Case("v14", AArch64::Q14)
> .Case("v15", AArch64::Q15)
> .Case("v16", AArch64::Q16)
> .Case("v17", AArch64::Q17)
> .Case("v18", AArch64::Q18)
> .Case("v19", AArch64::Q19)
> .Case("v20", AArch64::Q20)
> .Case("v21", AArch64::Q21)
> .Case("v22", AArch64::Q22)
> .Case("v23", AArch64::Q23)
> .Case("v24", AArch64::Q24)
> .Case("v25", AArch64::Q25)
> .Case("v26", AArch64::Q26)
> .Case("v27", AArch64::Q27)
> .Case("v28", AArch64::Q28)
> .Case("v29", AArch64::Q29)
> .Case("v30", AArch64::Q30)
> .Case("v31", AArch64::Q31)
> .Default(0);
>
> Which is a little bit redundant as this is all specified in TableGen.
>
> let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
> def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>;
> def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>;
> def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>;
> def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>;
> def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>;
> def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>;
> def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>;
> def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>;
> def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>;
> def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>;
> def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
> def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>;
> def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
> def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
> def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>;
> def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
> def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
> def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
> def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
> def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>;
> def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
> def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
> def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
> def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
> def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
> def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
> def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
> def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
> def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>;
> def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
> def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
> def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
>
>
>
> On Wed, Jun 17, 2015 at 2:21 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
> wrote:
>
>> +Jim, Owen
>>
>> Don’t we already have a mechanism for register name aliases, or am I
>> mistaken?
>>
>> Thanks,
>> /jakob
>>
>> On Jun 16, 2015, at 8:08 AM, Dylan McKay <dylanmckay34 at gmail.com> wrote:
>>
>> This commit adds a new flag ShouldEmitMatchRegisterAltName to
>> include/Target/Target.td, and generates an alternative register name
>> matching function named MatchRegisterAlias to the generated AsmMatcher
>> if it is enabled.
>>
>> Backends can use this to parse alternative register names based on values
>> stored
>> in TableGen files. The AVR-LLVM <https://github.com/avr-llvm/llvm>
>> project is using this function to parse special pointer registers,
>> identified by X, Y, and Z, which are alternative names to the GPR pairs
>> r27:r26, r29:r28, and r31:r30.
>>
>> Files changed:
>>
>> - include/Target/Target.td
>> - utils/TableGen/AsmMatcherEmitter.cpp
>>
>>
>> <0001-TableGen-Add-MatchRegisterAltName-to-AsmMatcher.patch>
>>
>>
>>
>
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