[llvm] r239657 - R600 -> AMDGPU rename
Tom Stellard
thomas.stellard at amd.com
Fri Jun 12 20:28:16 PDT 2015
Copied: llvm/trunk/test/CodeGen/AMDGPU/smrd.ll (from r239647, llvm/trunk/test/CodeGen/R600/smrd.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smrd.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/smrd.ll&p1=llvm/trunk/test/CodeGen/R600/smrd.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/split-scalar-i64-add.ll (from r239647, llvm/trunk/test/CodeGen/R600/split-scalar-i64-add.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/split-scalar-i64-add.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/split-scalar-i64-add.ll&p1=llvm/trunk/test/CodeGen/R600/split-scalar-i64-add.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/sra.ll (from r239647, llvm/trunk/test/CodeGen/R600/sra.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sra.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/sra.ll&p1=llvm/trunk/test/CodeGen/R600/sra.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/srem.ll (from r239647, llvm/trunk/test/CodeGen/R600/srem.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/srem.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/srem.ll&p1=llvm/trunk/test/CodeGen/R600/srem.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/srl.ll (from r239647, llvm/trunk/test/CodeGen/R600/srl.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/srl.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/srl.ll&p1=llvm/trunk/test/CodeGen/R600/srl.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/ssubo.ll (from r239647, llvm/trunk/test/CodeGen/R600/ssubo.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ssubo.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/ssubo.ll&p1=llvm/trunk/test/CodeGen/R600/ssubo.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store-barrier.ll (from r239647, llvm/trunk/test/CodeGen/R600/store-barrier.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-barrier.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store-barrier.ll&p1=llvm/trunk/test/CodeGen/R600/store-barrier.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store-v3i32.ll (from r239647, llvm/trunk/test/CodeGen/R600/store-v3i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-v3i32.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store-v3i32.ll&p1=llvm/trunk/test/CodeGen/R600/store-v3i32.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store-v3i64.ll (from r239647, llvm/trunk/test/CodeGen/R600/store-v3i64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-v3i64.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store-v3i64.ll&p1=llvm/trunk/test/CodeGen/R600/store-v3i64.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store-vector-ptrs.ll (from r239647, llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store-vector-ptrs.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store-vector-ptrs.ll&p1=llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store.ll (from r239647, llvm/trunk/test/CodeGen/R600/store.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store.ll&p1=llvm/trunk/test/CodeGen/R600/store.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/store.r600.ll (from r239647, llvm/trunk/test/CodeGen/R600/store.r600.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/store.r600.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/store.r600.ll&p1=llvm/trunk/test/CodeGen/R600/store.r600.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/structurize.ll (from r239647, llvm/trunk/test/CodeGen/R600/structurize.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/structurize.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/structurize.ll&p1=llvm/trunk/test/CodeGen/R600/structurize.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll (from r239647, llvm/trunk/test/CodeGen/R600/structurize1.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/structurize1.ll&p1=llvm/trunk/test/CodeGen/R600/structurize1.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/sub.ll (from r239647, llvm/trunk/test/CodeGen/R600/sub.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sub.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/sub.ll&p1=llvm/trunk/test/CodeGen/R600/sub.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll (from r239647, llvm/trunk/test/CodeGen/R600/subreg-coalescer-crash.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll&p1=llvm/trunk/test/CodeGen/R600/subreg-coalescer-crash.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll (from r239647, llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll&p1=llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/swizzle-export.ll (from r239647, llvm/trunk/test/CodeGen/R600/swizzle-export.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/swizzle-export.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/swizzle-export.ll&p1=llvm/trunk/test/CodeGen/R600/swizzle-export.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/tex-clause-antidep.ll (from r239647, llvm/trunk/test/CodeGen/R600/tex-clause-antidep.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/tex-clause-antidep.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/tex-clause-antidep.ll&p1=llvm/trunk/test/CodeGen/R600/tex-clause-antidep.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/texture-input-merge.ll (from r239647, llvm/trunk/test/CodeGen/R600/texture-input-merge.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/texture-input-merge.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/texture-input-merge.ll&p1=llvm/trunk/test/CodeGen/R600/texture-input-merge.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/trunc-cmp-constant.ll (from r239647, llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc-cmp-constant.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/trunc-cmp-constant.ll&p1=llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll (from r239647, llvm/trunk/test/CodeGen/R600/trunc-store-f64-to-f16.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll&p1=llvm/trunk/test/CodeGen/R600/trunc-store-f64-to-f16.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/trunc-store-i1.ll (from r239647, llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc-store-i1.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/trunc-store-i1.ll&p1=llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll (from r239647, llvm/trunk/test/CodeGen/R600/trunc-vector-store-assertion-failure.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll&p1=llvm/trunk/test/CodeGen/R600/trunc-vector-store-assertion-failure.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/trunc.ll (from r239647, llvm/trunk/test/CodeGen/R600/trunc.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/trunc.ll&p1=llvm/trunk/test/CodeGen/R600/trunc.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/tti-unroll-prefs.ll (from r239647, llvm/trunk/test/CodeGen/R600/tti-unroll-prefs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/tti-unroll-prefs.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/tti-unroll-prefs.ll&p1=llvm/trunk/test/CodeGen/R600/tti-unroll-prefs.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll (from r239647, llvm/trunk/test/CodeGen/R600/uaddo.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll&p1=llvm/trunk/test/CodeGen/R600/uaddo.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/udiv.ll (from r239647, llvm/trunk/test/CodeGen/R600/udiv.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/udiv.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/udiv.ll&p1=llvm/trunk/test/CodeGen/R600/udiv.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/udivrem.ll (from r239647, llvm/trunk/test/CodeGen/R600/udivrem.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/udivrem.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/udivrem.ll&p1=llvm/trunk/test/CodeGen/R600/udivrem.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll (from r239647, llvm/trunk/test/CodeGen/R600/udivrem24.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll&p1=llvm/trunk/test/CodeGen/R600/udivrem24.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/udivrem64.ll (from r239647, llvm/trunk/test/CodeGen/R600/udivrem64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/udivrem64.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/udivrem64.ll&p1=llvm/trunk/test/CodeGen/R600/udivrem64.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.f64.ll (from r239647, llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.f64.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.f64.ll&p1=llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.ll (from r239647, llvm/trunk/test/CodeGen/R600/uint_to_fp.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/uint_to_fp.ll&p1=llvm/trunk/test/CodeGen/R600/uint_to_fp.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/unaligned-load-store.ll (from r239647, llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unaligned-load-store.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/unaligned-load-store.ll&p1=llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll (from r239647, llvm/trunk/test/CodeGen/R600/unhandled-loop-condition-assertion.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll&p1=llvm/trunk/test/CodeGen/R600/unhandled-loop-condition-assertion.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/unroll.ll (from r239647, llvm/trunk/test/CodeGen/R600/unroll.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unroll.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/unroll.ll&p1=llvm/trunk/test/CodeGen/R600/unroll.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/unsupported-cc.ll (from r239647, llvm/trunk/test/CodeGen/R600/unsupported-cc.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unsupported-cc.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/unsupported-cc.ll&p1=llvm/trunk/test/CodeGen/R600/unsupported-cc.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/urecip.ll (from r239647, llvm/trunk/test/CodeGen/R600/urecip.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/urecip.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/urecip.ll&p1=llvm/trunk/test/CodeGen/R600/urecip.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/urem.ll (from r239647, llvm/trunk/test/CodeGen/R600/urem.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/urem.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/urem.ll&p1=llvm/trunk/test/CodeGen/R600/urem.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll (from r239647, llvm/trunk/test/CodeGen/R600/use-sgpr-multiple-times.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll&p1=llvm/trunk/test/CodeGen/R600/use-sgpr-multiple-times.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/usubo.ll (from r239647, llvm/trunk/test/CodeGen/R600/usubo.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/usubo.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/usubo.ll&p1=llvm/trunk/test/CodeGen/R600/usubo.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/v1i64-kernel-arg.ll (from r239647, llvm/trunk/test/CodeGen/R600/v1i64-kernel-arg.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/v1i64-kernel-arg.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/v1i64-kernel-arg.ll&p1=llvm/trunk/test/CodeGen/R600/v1i64-kernel-arg.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll (from r239647, llvm/trunk/test/CodeGen/R600/v_cndmask.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/v_cndmask.ll&p1=llvm/trunk/test/CodeGen/R600/v_cndmask.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll (from r239647, llvm/trunk/test/CodeGen/R600/valu-i1.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll&p1=llvm/trunk/test/CodeGen/R600/valu-i1.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/vector-alloca.ll (from r239647, llvm/trunk/test/CodeGen/R600/vector-alloca.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vector-alloca.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vector-alloca.ll&p1=llvm/trunk/test/CodeGen/R600/vector-alloca.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll (from r239647, llvm/trunk/test/CodeGen/R600/vertex-fetch-encoding.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll&p1=llvm/trunk/test/CodeGen/R600/vertex-fetch-encoding.ll&r1=239647&r2=239657&rev=239657&view=diff
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Copied: llvm/trunk/test/CodeGen/AMDGPU/vop-shrink.ll (from r239647, llvm/trunk/test/CodeGen/R600/vop-shrink.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vop-shrink.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vop-shrink.ll&p1=llvm/trunk/test/CodeGen/R600/vop-shrink.ll&r1=239647&r2=239657&rev=239657&view=diff
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(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/vselect.ll (from r239647, llvm/trunk/test/CodeGen/R600/vselect.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vselect.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vselect.ll&p1=llvm/trunk/test/CodeGen/R600/vselect.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/vselect64.ll (from r239647, llvm/trunk/test/CodeGen/R600/vselect64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vselect64.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vselect64.ll&p1=llvm/trunk/test/CodeGen/R600/vselect64.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/vtx-fetch-branch.ll (from r239647, llvm/trunk/test/CodeGen/R600/vtx-fetch-branch.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vtx-fetch-branch.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vtx-fetch-branch.ll&p1=llvm/trunk/test/CodeGen/R600/vtx-fetch-branch.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/vtx-schedule.ll (from r239647, llvm/trunk/test/CodeGen/R600/vtx-schedule.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vtx-schedule.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/vtx-schedule.ll&p1=llvm/trunk/test/CodeGen/R600/vtx-schedule.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/wait.ll (from r239647, llvm/trunk/test/CodeGen/R600/wait.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wait.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/wait.ll&p1=llvm/trunk/test/CodeGen/R600/wait.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/work-item-intrinsics.ll (from r239647, llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/work-item-intrinsics.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/work-item-intrinsics.ll&p1=llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll (from r239647, llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll&p1=llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/xor.ll (from r239647, llvm/trunk/test/CodeGen/R600/xor.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/xor.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/xor.ll&p1=llvm/trunk/test/CodeGen/R600/xor.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/AMDGPU/zero_extend.ll (from r239647, llvm/trunk/test/CodeGen/R600/zero_extend.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/zero_extend.ll?p2=llvm/trunk/test/CodeGen/AMDGPU/zero_extend.ll&p1=llvm/trunk/test/CodeGen/R600/zero_extend.ll&r1=239647&r2=239657&rev=239657&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll (removed)
@@ -1,139 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
-; the global address space(1) uses 64-bit pointers. These tests check to make sure
-; the correct pointer size is used for the local address space.
-
-; The e{{32|64}} suffix on the instructions refers to the encoding size and not
-; the size of the operands. The operand size is denoted in the instruction name.
-; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
-; instructions with B64, U64, and I64 take 64-bit operands.
-
-; FUNC-LABEL: {{^}}local_address_load:
-; SI: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]]
-; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
-define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
- %0 = load i32, i32 addrspace(3)* %in
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep:
-; SI: s_add_i32 [[SPTR:s[0-9]]]
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_read_b32 [[VPTR]]
-define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
-entry:
- %0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset
- %1 = load i32, i32 addrspace(3)* %0
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_const_offset:
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
-; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
-define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
- %0 = getelementptr i32, i32 addrspace(3)* %in, i32 1
- %1 = load i32, i32 addrspace(3)* %0
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
-
-; Offset too large, can't fold into 16-bit immediate offset.
-; FUNC-LABEL: {{^}}local_address_gep_large_const_offset:
-; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_read_b32 [[VPTR]]
-define void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
-entry:
- %0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385
- %1 = load i32, i32 addrspace(3)* %0
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}null_32bit_lds_ptr:
-; SI: v_cmp_ne_i32
-; SI-NOT: v_cmp_ne_i32
-; SI: v_cndmask_b32
-define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind {
- %cmp = icmp ne i32 addrspace(3)* %lds, null
- %x = select i1 %cmp, i32 123, i32 456
- store i32 %x, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}mul_32bit_ptr:
-; SI: s_mul_i32
-; SI-NEXT: s_add_i32
-; SI: ds_read_b32
-define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
- %ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
- %val = load float, float addrspace(3)* %ptr
- store float %val, float addrspace(1)* %out
- ret void
-}
-
- at g_lds = addrspace(3) global float undef, align 4
-
-; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: ds_read_b32 v{{[0-9]+}}, [[REG]]
-define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
- %val = load float, float addrspace(3)* @g_lds
- store float %val, float addrspace(1)* %out
- ret void
-}
-
-
- at ptr = addrspace(3) global i32 addrspace(3)* undef
- at dst = addrspace(3) global [16384 x i32] undef
-
-; FUNC-LABEL: {{^}}global_ptr:
-; SI: ds_write_b32
-define void @global_ptr() nounwind {
- store i32 addrspace(3)* getelementptr ([16384 x i32], [16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
- ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_store:
-; SI: ds_write_b32
-define void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
- store i32 %val, i32 addrspace(3)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_store:
-; SI: s_add_i32 [[SADDR:s[0-9]+]],
-; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
-; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}}
-define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
- %gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset
- store i32 %val, i32 addrspace(3)* %gep, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}local_address_gep_const_offset_store:
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
-; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
-; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
-define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
- %gep = getelementptr i32, i32 addrspace(3)* %out, i32 1
- store i32 %val, i32 addrspace(3)* %gep, align 4
- ret void
-}
-
-; Offset too large, can't fold into 16-bit immediate offset.
-; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
-; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
-; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
-; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
-define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
- %gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385
- store i32 %val, i32 addrspace(3)* %gep, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/README
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/README?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/README (original)
+++ llvm/trunk/test/CodeGen/R600/README (removed)
@@ -1,21 +0,0 @@
-+==============================================================================+
-| How to organize the lit tests |
-+==============================================================================+
-
-- If you write a test for matching a single DAG opcode or intrinsic, it should
- go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)
-
-- If you write a test that matches several DAG opcodes and checks for a single
- ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
- bfi_int.ll
-
-- For all other tests, use your best judgement for organizing tests and naming
- the files.
-
-+==============================================================================+
-| Naming conventions |
-+==============================================================================+
-
-- Use dash '-' and not underscore '_' to separate words in file names, unless
- the file is named after a DAG opcode or ISA instruction that has an
- underscore '_' in its name.
Removed: llvm/trunk/test/CodeGen/R600/add-debug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add-debug.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add-debug.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add-debug.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tahiti -debug
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -debug
-; REQUIRES: asserts
-
-; Check that SelectionDAGDumper does not crash on int_SI_if.
-define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
-entry:
- %0 = icmp eq i64 %a, 0
- br i1 %0, label %if, label %else
-
-if:
- %1 = load i64, i64 addrspace(1)* %in
- br label %endif
-
-else:
- %2 = add i64 %a, %b
- br label %endif
-
-endif:
- %3 = phi i64 [%1, %if], [%2, %else]
- store i64 %3, i64 addrspace(1)* %out
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add.ll (removed)
@@ -1,192 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-
-;FUNC-LABEL: {{^}}test1:
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-;SI: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
-;SI-NOT: [[REG]]
-;SI: buffer_store_dword [[REG]],
-define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
- %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %a = load i32, i32 addrspace(1)* %in
- %b = load i32, i32 addrspace(1)* %b_ptr
- %result = add i32 %a, %b
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
-
-;FUNC-LABEL: {{^}}test2:
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
-define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
- %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
- %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
- %result = add <2 x i32> %a, %b
- store <2 x i32> %result, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-;FUNC-LABEL: {{^}}test4:
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-;SI: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
-define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
- %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
- %result = add <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test8:
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
-entry:
- %0 = add <8 x i32> %a, %b
- store <8 x i32> %0, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test16:
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-; EG: ADD_INT
-
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-; SI: s_add_i32
-define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
-entry:
- %0 = add <16 x i32> %a, %b
- store <16 x i32> %0, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}add64:
-; SI: s_add_u32
-; SI: s_addc_u32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
-; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
-; EG-DAG: ADDC_UINT
-; EG-DAG: ADD_INT
-; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
-; EG-NOT: SUB
-define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
-entry:
- %0 = add i64 %a, %b
- store i64 %0, i64 addrspace(1)* %out
- ret void
-}
-
-; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
-; use VCC. The test is designed so that %a will be stored in an SGPR and
-; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
-; to a VGPR before doing the add.
-
-; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
-; SI-NOT: v_addc_u32_e32 s
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
-; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
-; EG-DAG: ADDC_UINT
-; EG-DAG: ADD_INT
-; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
-; EG-NOT: SUB
-define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
-entry:
- %0 = load i64, i64 addrspace(1)* %in
- %1 = add i64 %a, %0
- store i64 %1, i64 addrspace(1)* %out
- ret void
-}
-
-; Test i64 add inside a branch.
-; FUNC-LABEL: {{^}}add64_in_branch:
-; SI: s_add_u32
-; SI: s_addc_u32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
-; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
-; EG-DAG: ADDC_UINT
-; EG-DAG: ADD_INT
-; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
-; EG-NOT: SUB
-define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
-entry:
- %0 = icmp eq i64 %a, 0
- br i1 %0, label %if, label %else
-
-if:
- %1 = load i64, i64 addrspace(1)* %in
- br label %endif
-
-else:
- %2 = add i64 %a, %b
- br label %endif
-
-endif:
- %3 = phi i64 [%1, %if], [%2, %else]
- store i64 %3, i64 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/add_i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add_i64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add_i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add_i64.ll (removed)
@@ -1,84 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
-
-
-declare i32 @llvm.r600.read.tidig.x() readnone
-
-; SI-LABEL: {{^}}test_i64_vreg:
-; SI: v_add_i32
-; SI: v_addc_u32
-define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
- %tid = call i32 @llvm.r600.read.tidig.x() readnone
- %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
- %b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
- %a = load i64, i64 addrspace(1)* %a_ptr
- %b = load i64, i64 addrspace(1)* %b_ptr
- %result = add i64 %a, %b
- store i64 %result, i64 addrspace(1)* %out
- ret void
-}
-
-; Check that the SGPR add operand is correctly moved to a VGPR.
-; SI-LABEL: {{^}}sgpr_operand:
-; SI: v_add_i32
-; SI: v_addc_u32
-define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
- %foo = load i64, i64 addrspace(1)* %in, align 8
- %result = add i64 %foo, %a
- store i64 %result, i64 addrspace(1)* %out
- ret void
-}
-
-; Swap the arguments. Check that the SGPR -> VGPR copy works with the
-; SGPR as other operand.
-;
-; SI-LABEL: {{^}}sgpr_operand_reversed:
-; SI: v_add_i32
-; SI: v_addc_u32
-define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
- %foo = load i64, i64 addrspace(1)* %in, align 8
- %result = add i64 %a, %foo
- store i64 %result, i64 addrspace(1)* %out
- ret void
-}
-
-
-; SI-LABEL: {{^}}test_v2i64_sreg:
-; SI: s_add_u32
-; SI: s_addc_u32
-; SI: s_add_u32
-; SI: s_addc_u32
-define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
- %result = add <2 x i64> %a, %b
- store <2 x i64> %result, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}test_v2i64_vreg:
-; SI: v_add_i32
-; SI: v_addc_u32
-; SI: v_add_i32
-; SI: v_addc_u32
-define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
- %tid = call i32 @llvm.r600.read.tidig.x() readnone
- %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
- %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
- %a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
- %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
- %result = add <2 x i64> %a, %b
- store <2 x i64> %result, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}trunc_i64_add_to_i32:
-; SI: s_load_dword s[[SREG0:[0-9]+]]
-; SI: s_load_dword s[[SREG1:[0-9]+]]
-; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
-; SI-NOT: addc
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
- %add = add i64 %b, %a
- %trunc = trunc i64 %add to i32
- store i32 %trunc, i32 addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/address-space.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/address-space.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-
-; Test that codegenprepare understands address space sizes
-
-%struct.foo = type { [3 x float], [3 x float] }
-
-; FIXME: Extra V_MOV from SGPR to VGPR for second read. The address is
-; already in a VGPR after the first read.
-
-; CHECK-LABEL: {{^}}do_as_ptr_calcs:
-; CHECK: s_load_dword [[SREG1:s[0-9]+]],
-; CHECK: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG1]]
-; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
-; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12
-; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG2]] offset:20
-define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind {
-entry:
- %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0
- %y = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2
- br label %bb32
-
-bb32:
- %a = load float, float addrspace(3)* %x, align 4
- %b = load float, float addrspace(3)* %y, align 4
- %cmp = fcmp one float %a, %b
- br i1 %cmp, label %bb34, label %bb33
-
-bb33:
- unreachable
-
-bb34:
- unreachable
-}
-
-
Removed: llvm/trunk/test/CodeGen/R600/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/and.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/and.ll (original)
+++ llvm/trunk/test/CodeGen/R600/and.ll (removed)
@@ -1,296 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test2:
-; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
-define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
- %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
- %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
- %result = and <2 x i32> %a, %b
- store <2 x i32> %result, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test4:
-; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-
-define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
- %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
- %result = and <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_i32:
-; SI: s_and_b32
-define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
- %and = and i32 %a, %b
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_constant_i32:
-; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
-define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
- %and = and i32 %a, 1234567
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_i32:
-; SI: v_and_b32
-define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
- %a = load i32, i32 addrspace(1)* %aptr, align 4
- %b = load i32, i32 addrspace(1)* %bptr, align 4
- %and = and i32 %a, %b
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_constant_i32
-; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
-define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
- %a = load i32, i32 addrspace(1)* %aptr, align 4
- %and = and i32 %a, 1234567
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
-; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
-define void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
- %a = load i32, i32 addrspace(1)* %aptr, align 4
- %and = and i32 %a, 64
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
-; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
-define void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
- %a = load i32, i32 addrspace(1)* %aptr, align 4
- %and = and i32 %a, -16
- store i32 %and, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_i64
-; SI: s_and_b64
-define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
- %and = and i64 %a, %b
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FIXME: Should use SGPRs
-; FUNC-LABEL: {{^}}s_and_i1:
-; SI: v_and_b32
-define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
- %and = and i1 %a, %b
- store i1 %and, i1 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_constant_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
-define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
- %and = and i64 %a, 281474976710655
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_i64:
-; SI: v_and_b32
-; SI: v_and_b32
-define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
- %a = load i64, i64 addrspace(1)* %aptr, align 8
- %b = load i64, i64 addrspace(1)* %bptr, align 8
- %and = and i64 %a, %b
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_i64_br:
-; SI: v_and_b32
-; SI: v_and_b32
-define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) {
-entry:
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %if, label %endif
-
-if:
- %a = load i64, i64 addrspace(1)* %aptr, align 8
- %b = load i64, i64 addrspace(1)* %bptr, align 8
- %and = and i64 %a, %b
- br label %endif
-
-endif:
- %tmp1 = phi i64 [%and, %if], [0, %entry]
- store i64 %tmp1, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_and_constant_i64:
-; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
-; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
-define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
- %a = load i64, i64 addrspace(1)* %aptr, align 8
- %and = and i64 %a, 1234567
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FIXME: Replace and 0 with mov 0
-; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
-; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
-; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
-define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
- %a = load i64, i64 addrspace(1)* %aptr, align 8
- %and = and i64 %a, 64
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64
-define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 64
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1
-define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 1
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
-define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 4607182418800017408
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
-define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 13830554455654793216
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
-define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 4602678819172646912
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
-define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 13826050856027422720
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0
-define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 4611686018427387904
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0
-define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 13835058055282163712
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
-define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 4616189618054758400
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
-define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 13839561654909534208
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-
-; Test with the 64-bit integer bitpattern for a 32-bit float in the
-; low 32-bits, which is not a valid 64-bit inline immmediate.
-
-; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64
-; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
-; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
-define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 1082130432
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FIXME: Copy of -1 register
-; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64
-; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
-; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
-; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}
-define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, -1065353216
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; Shift into upper 32-bits
-; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64
-; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
-; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
-define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 4647714815446351872
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64
-; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
-; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
-; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
-define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
- %and = and i64 %a, 13871086852301127680
- store i64 %and, i64 addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/anyext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/anyext.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/anyext.ll (original)
+++ llvm/trunk/test/CodeGen/R600/anyext.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; CHECK-LABEL: {{^}}anyext_i1_i32:
-; CHECK: v_cndmask_b32_e64
-define void @anyext_i1_i32(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp eq i32 %cond, 0
- %1 = zext i1 %0 to i8
- %2 = xor i8 %1, -1
- %3 = and i8 %2, 1
- %4 = zext i8 %3 to i32
- store i32 %4, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/array-ptr-calc-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/array-ptr-calc-i32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/array-ptr-calc-i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/array-ptr-calc-i32.ll (removed)
@@ -1,44 +0,0 @@
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
-
-declare i32 @llvm.SI.tid() nounwind readnone
-declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
-
-; The required pointer calculations for the alloca'd actually requires
-; an add and won't be folded into the addressing, which fails with a
-; 64-bit pointer add. This should work since private pointers should
-; be 32-bits.
-
-; SI-LABEL: {{^}}test_private_array_ptr_calc:
-
-; FIXME: We end up with zero argument for ADD, because
-; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index
-; with the appropriate offset. We should fold this into the store.
-; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], 0, v{{[0-9]+}}
-; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}]
-;
-; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
-; alloca to a vector. It currently fails because it does not know how
-; to interpret:
-; getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
-
-; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], 16
-; SI-PROMOTE: ds_write_b32 [[PTRREG]]
-define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
- %alloca = alloca [4 x i32], i32 4, align 16
- %tid = call i32 @llvm.SI.tid() readnone
- %a_ptr = getelementptr i32, i32 addrspace(1)* %inA, i32 %tid
- %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid
- %a = load i32, i32 addrspace(1)* %a_ptr
- %b = load i32, i32 addrspace(1)* %b_ptr
- %result = add i32 %a, %b
- %alloca_ptr = getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
- store i32 %result, i32* %alloca_ptr, align 4
- ; Dummy call
- call void @llvm.AMDGPU.barrier.local() nounwind noduplicate
- %reload = load i32, i32* %alloca_ptr, align 4
- %out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare i32 @llvm.SI.tid() readnone
-
-; SI-LABEL: {{^}}test_array_ptr_calc:
-; SI: v_mul_lo_i32
-; SI: v_mul_hi_i32
-define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
- %tid = call i32 @llvm.SI.tid() readnone
- %a_ptr = getelementptr [1025 x i32], [1025 x i32] addrspace(1)* %inA, i32 %tid, i32 0
- %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid
- %a = load i32, i32 addrspace(1)* %a_ptr
- %b = load i32, i32 addrspace(1)* %b_ptr
- %result = add i32 %a, %b
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/atomic_cmp_swap_local.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/atomic_cmp_swap_local.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/atomic_cmp_swap_local.ll (original)
+++ llvm/trunk/test/CodeGen/R600/atomic_cmp_swap_local.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SICI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SICI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
-; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
-; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
-; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
-; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
-; GCN: s_endpgm
-define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap) nounwind {
- %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
- %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
- %result = extractvalue { i32, i1 } %pair, 0
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
-; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
-; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
-; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
-; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
-; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
-; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
-; GCN: buffer_store_dwordx2 [[RESULT]],
-; GCN: s_endpgm
-define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
- %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
- %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
- %result = extractvalue { i64, i1 } %pair, 0
- store i64 %result, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
-; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
-; GCN: s_endpgm
-define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
- %sub = sub i32 %a, %b
- %add = add i32 %sub, 4
- %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
- %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
- %result = extractvalue { i32, i1 } %pair, 0
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset:
-; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
-; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa
-; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
-; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28
-; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
-; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
-; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
-; GCN: s_endpgm
-define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %swap) nounwind {
- %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
- %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
- %result = extractvalue { i32, i1 } %pair, 0
- ret void
-}
-
-; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
-; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
-; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
-; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
-; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
-; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
-; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
-; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
-; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
-; GCN: s_endpgm
-define void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
- %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
- %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
- %result = extractvalue { i64, i1 } %pair, 0
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/atomic_load_add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/atomic_load_add.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/atomic_load_add.ll (original)
+++ llvm/trunk/test/CodeGen/R600/atomic_load_add.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}atomic_add_local:
-; R600: LDS_ADD *
-; SI: ds_add_u32
-define void @atomic_add_local(i32 addrspace(3)* %local) {
- %unused = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_local_const_offset:
-; R600: LDS_ADD *
-; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-define void @atomic_add_local_const_offset(i32 addrspace(3)* %local) {
- %gep = getelementptr i32, i32 addrspace(3)* %local, i32 4
- %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_ret_local:
-; R600: LDS_ADD_RET *
-; SI: ds_add_rtn_u32
-define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
- %val = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
- store i32 %val, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_ret_local_const_offset:
-; R600: LDS_ADD_RET *
-; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
-define void @atomic_add_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
- %gep = getelementptr i32, i32 addrspace(3)* %local, i32 5
- %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
- store i32 %val, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll (original)
+++ llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}atomic_sub_local:
-; R600: LDS_SUB *
-; SI: ds_sub_u32
-define void @atomic_sub_local(i32 addrspace(3)* %local) {
- %unused = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_local_const_offset:
-; R600: LDS_SUB *
-; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
-define void @atomic_sub_local_const_offset(i32 addrspace(3)* %local) {
- %gep = getelementptr i32, i32 addrspace(3)* %local, i32 4
- %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_ret_local:
-; R600: LDS_SUB_RET *
-; SI: ds_sub_rtn_u32
-define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
- %val = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
- store i32 %val, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_ret_local_const_offset:
-; R600: LDS_SUB_RET *
-; SI: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
-define void @atomic_sub_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
- %gep = getelementptr i32, i32 addrspace(3)* %local, i32 5
- %val = atomicrmw volatile sub i32 addrspace(3)* %gep, i32 5 seq_cst
- store i32 %val, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/basic-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/basic-branch.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/basic-branch.ll (original)
+++ llvm/trunk/test/CodeGen/R600/basic-branch.ll (removed)
@@ -1,16 +0,0 @@
-; XFAIL: *
-; RUN: llc -O0 -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-
-; CHECK-LABEL: {{^}}test_branch(
-define void @test_branch(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) nounwind {
- %cmp = icmp ne i32 %val, 0
- br i1 %cmp, label %store, label %end
-
-store:
- store i32 222, i32 addrspace(1)* %out
- ret void
-
-end:
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/basic-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/basic-loop.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/basic-loop.ll (original)
+++ llvm/trunk/test/CodeGen/R600/basic-loop.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
-; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s
-
-; CHECK-LABEL: {{^}}test_loop:
-define void @test_loop(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) nounwind {
-entry:
- br label %loop.body
-
-loop.body:
- %i = phi i32 [0, %entry], [%i.inc, %loop.body]
- store i32 222, i32 addrspace(1)* %out
- %cmp = icmp ne i32 %i, %val
- %i.inc = add i32 %i, 1
- br i1 %cmp, label %loop.body, label %end
-
-end:
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/bfe_uint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/bfe_uint.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/bfe_uint.ll (original)
+++ llvm/trunk/test/CodeGen/R600/bfe_uint.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}bfe_def:
-; CHECK: BFE_UINT
-define void @bfe_def(i32 addrspace(1)* %out, i32 %x) {
-entry:
- %0 = lshr i32 %x, 5
- %1 = and i32 %0, 15 ; 0xf
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
-
-; This program could be implemented using a BFE_UINT instruction, however
-; since the lshr constant + number of bits in the mask is >= 32, it can also be
-; implmented with a LSHR instruction, which is better, because LSHR has less
-; operands and requires less constants.
-
-; CHECK: {{^}}bfe_shift:
-; CHECK-NOT: BFE_UINT
-define void @bfe_shift(i32 addrspace(1)* %out, i32 %x) {
-entry:
- %0 = lshr i32 %x, 16
- %1 = and i32 %0, 65535 ; 0xffff
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/bfi_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/bfi_int.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/bfi_int.ll (original)
+++ llvm/trunk/test/CodeGen/R600/bfi_int.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s
-
-; BFI_INT Definition pattern from ISA docs
-; (y & x) | (z & ~x)
-;
-; R600: {{^}}bfi_def:
-; R600: BFI_INT
-; SI: @bfi_def
-; SI: v_bfi_b32
-define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
-entry:
- %0 = xor i32 %x, -1
- %1 = and i32 %z, %0
- %2 = and i32 %y, %x
- %3 = or i32 %1, %2
- store i32 %3, i32 addrspace(1)* %out
- ret void
-}
-
-; SHA-256 Ch function
-; z ^ (x & (y ^ z))
-; R600: {{^}}bfi_sha256_ch:
-; R600: BFI_INT
-; SI: @bfi_sha256_ch
-; SI: v_bfi_b32
-define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
-entry:
- %0 = xor i32 %y, %z
- %1 = and i32 %x, %0
- %2 = xor i32 %z, %1
- store i32 %2, i32 addrspace(1)* %out
- ret void
-}
-
-; SHA-256 Ma function
-; ((x & z) | (y & (x | z)))
-; R600: {{^}}bfi_sha256_ma:
-; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
-; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
-; SI: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}}
-; SI: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}}
-
-define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
-entry:
- %0 = and i32 %x, %z
- %1 = or i32 %x, %z
- %2 = and i32 %y, %1
- %3 = or i32 %0, %2
- store i32 %3, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/big_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/big_alu.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/big_alu.ll (original)
+++ llvm/trunk/test/CodeGen/R600/big_alu.ll (removed)
@@ -1,1173 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=cedar
-
-;This test ensures that R600 backend can handle ifcvt properly
-;and do not generate ALU clauses with more than 128 instructions.
-
-define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #0 {
-main_body:
- %0 = extractelement <4 x float> %reg0, i32 0
- %1 = extractelement <4 x float> %reg0, i32 1
- %2 = extractelement <4 x float> %reg0, i32 2
- %3 = extractelement <4 x float> %reg0, i32 3
- %4 = extractelement <4 x float> %reg1, i32 0
- %5 = extractelement <4 x float> %reg9, i32 0
- %6 = extractelement <4 x float> %reg8, i32 0
- %7 = fcmp ugt float %6, 0.000000e+00
- %8 = select i1 %7, float %4, float %5
- %9 = extractelement <4 x float> %reg1, i32 1
- %10 = extractelement <4 x float> %reg9, i32 1
- %11 = extractelement <4 x float> %reg8, i32 0
- %12 = fcmp ugt float %11, 0.000000e+00
- %13 = select i1 %12, float %9, float %10
- %14 = extractelement <4 x float> %reg1, i32 2
- %15 = extractelement <4 x float> %reg9, i32 2
- %16 = extractelement <4 x float> %reg8, i32 0
- %17 = fcmp ugt float %16, 0.000000e+00
- %18 = select i1 %17, float %14, float %15
- %19 = extractelement <4 x float> %reg1, i32 3
- %20 = extractelement <4 x float> %reg9, i32 3
- %21 = extractelement <4 x float> %reg8, i32 0
- %22 = extractelement <4 x float> %reg2, i32 0
- %23 = extractelement <4 x float> %reg2, i32 1
- %24 = extractelement <4 x float> %reg2, i32 2
- %25 = extractelement <4 x float> %reg2, i32 3
- %26 = extractelement <4 x float> %reg3, i32 0
- %27 = extractelement <4 x float> %reg3, i32 1
- %28 = extractelement <4 x float> %reg3, i32 2
- %29 = extractelement <4 x float> %reg3, i32 3
- %30 = extractelement <4 x float> %reg4, i32 0
- %31 = extractelement <4 x float> %reg4, i32 1
- %32 = extractelement <4 x float> %reg4, i32 2
- %33 = extractelement <4 x float> %reg4, i32 3
- %34 = extractelement <4 x float> %reg5, i32 0
- %35 = extractelement <4 x float> %reg5, i32 1
- %36 = extractelement <4 x float> %reg5, i32 2
- %37 = extractelement <4 x float> %reg5, i32 3
- %38 = extractelement <4 x float> %reg6, i32 0
- %39 = extractelement <4 x float> %reg6, i32 1
- %40 = extractelement <4 x float> %reg6, i32 2
- %41 = extractelement <4 x float> %reg6, i32 3
- %42 = extractelement <4 x float> %reg7, i32 0
- %43 = extractelement <4 x float> %reg7, i32 1
- %44 = extractelement <4 x float> %reg7, i32 2
- %45 = extractelement <4 x float> %reg7, i32 3
- %46 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
- %47 = extractelement <4 x float> %46, i32 0
- %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
- %49 = extractelement <4 x float> %48, i32 1
- %50 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
- %51 = extractelement <4 x float> %50, i32 2
- %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
- %53 = extractelement <4 x float> %52, i32 0
- %54 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
- %55 = extractelement <4 x float> %54, i32 0
- %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
- %57 = extractelement <4 x float> %56, i32 1
- %58 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
- %59 = extractelement <4 x float> %58, i32 2
- %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
- %61 = extractelement <4 x float> %60, i32 3
- %62 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
- %63 = extractelement <4 x float> %62, i32 0
- %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
- %65 = extractelement <4 x float> %64, i32 1
- %66 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
- %67 = extractelement <4 x float> %66, i32 2
- %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %69 = extractelement <4 x float> %68, i32 0
- %70 = fcmp oge float %69, 3.500000e+00
- %71 = sext i1 %70 to i32
- %72 = bitcast i32 %71 to float
- %73 = bitcast float %72 to i32
- %74 = icmp ne i32 %73, 0
- %. = select i1 %74, float 0.000000e+00, float 0.000000e+00
- %75 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %76 = extractelement <4 x float> %75, i32 0
- %77 = fcmp oge float %76, 2.000000e+00
- %78 = sext i1 %77 to i32
- %79 = bitcast i32 %78 to float
- %80 = bitcast float %79 to i32
- %81 = icmp ne i32 %80, 0
- br i1 %81, label %IF137, label %ENDIF136
-
-IF137: ; preds = %main_body
- %82 = insertelement <4 x float> undef, float %30, i32 0
- %83 = insertelement <4 x float> %82, float %31, i32 1
- %84 = insertelement <4 x float> %83, float %32, i32 2
- %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3
- %86 = insertelement <4 x float> undef, float %30, i32 0
- %87 = insertelement <4 x float> %86, float %31, i32 1
- %88 = insertelement <4 x float> %87, float %32, i32 2
- %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3
- %90 = call float @llvm.AMDGPU.dp4(<4 x float> %85, <4 x float> %89)
- %91 = call float @llvm.AMDGPU.rsq.f32(float %90)
- %92 = fmul float %30, %91
- %93 = fmul float %31, %91
- %94 = fmul float %32, %91
- %95 = insertelement <4 x float> undef, float %92, i32 0
- %96 = insertelement <4 x float> %95, float %93, i32 1
- %97 = insertelement <4 x float> %96, float %94, i32 2
- %98 = insertelement <4 x float> %97, float 0.000000e+00, i32 3
- %99 = insertelement <4 x float> undef, float %37, i32 0
- %100 = insertelement <4 x float> %99, float %38, i32 1
- %101 = insertelement <4 x float> %100, float %39, i32 2
- %102 = insertelement <4 x float> %101, float 0.000000e+00, i32 3
- %103 = call float @llvm.AMDGPU.dp4(<4 x float> %98, <4 x float> %102)
- %104 = insertelement <4 x float> undef, float %92, i32 0
- %105 = insertelement <4 x float> %104, float %93, i32 1
- %106 = insertelement <4 x float> %105, float %94, i32 2
- %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3
- %108 = insertelement <4 x float> undef, float %40, i32 0
- %109 = insertelement <4 x float> %108, float %41, i32 1
- %110 = insertelement <4 x float> %109, float %42, i32 2
- %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3
- %112 = call float @llvm.AMDGPU.dp4(<4 x float> %107, <4 x float> %111)
- %113 = fsub float -0.000000e+00, %92
- %114 = fsub float -0.000000e+00, %93
- %115 = fsub float -0.000000e+00, %94
- %116 = insertelement <4 x float> undef, float %34, i32 0
- %117 = insertelement <4 x float> %116, float %35, i32 1
- %118 = insertelement <4 x float> %117, float %36, i32 2
- %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
- %120 = insertelement <4 x float> undef, float %113, i32 0
- %121 = insertelement <4 x float> %120, float %114, i32 1
- %122 = insertelement <4 x float> %121, float %115, i32 2
- %123 = insertelement <4 x float> %122, float 0.000000e+00, i32 3
- %124 = call float @llvm.AMDGPU.dp4(<4 x float> %119, <4 x float> %123)
- %125 = fdiv float 1.000000e+00, %124
- %126 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %127 = extractelement <4 x float> %126, i32 0
- %128 = fmul float %127, %125
- %129 = fmul float %103, %128
- %130 = fmul float %112, %128
- %131 = bitcast float %. to i32
- %132 = sitofp i32 %131 to float
- %133 = fdiv float 1.000000e+00, %132
- %134 = bitcast float %. to i32
- %135 = add i32 %134, -1
- %136 = bitcast i32 %135 to float
- %137 = bitcast float %136 to i32
- br label %LOOP
-
-ENDIF136: ; preds = %main_body, %ENDIF154
- %temp68.1 = phi float [ %600, %ENDIF154 ], [ 0.000000e+00, %main_body ]
- %temp69.0 = phi float [ %602, %ENDIF154 ], [ 0.000000e+00, %main_body ]
- %temp70.0 = phi float [ %604, %ENDIF154 ], [ 1.000000e+00, %main_body ]
- %138 = fmul float %26, 0x3F847AE140000000
- %139 = fmul float %27, 0x3F847AE140000000
- %140 = fmul float %28, 0x3F847AE140000000
- %141 = insertelement <4 x float> undef, float %138, i32 0
- %142 = insertelement <4 x float> %141, float %139, i32 1
- %143 = insertelement <4 x float> %142, float %140, i32 2
- %144 = insertelement <4 x float> %143, float 0.000000e+00, i32 3
- %145 = extractelement <4 x float> %144, i32 0
- %146 = extractelement <4 x float> %144, i32 1
- %147 = extractelement <4 x float> %144, i32 2
- %148 = extractelement <4 x float> %144, i32 3
- %149 = insertelement <4 x float> undef, float %145, i32 0
- %150 = insertelement <4 x float> %149, float %146, i32 1
- %151 = insertelement <4 x float> %150, float %147, i32 2
- %152 = insertelement <4 x float> %151, float %148, i32 3
- %153 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %152, i32 16, i32 0, i32 3)
- %154 = extractelement <4 x float> %153, i32 0
- %155 = extractelement <4 x float> %153, i32 1
- %156 = extractelement <4 x float> %153, i32 2
- %157 = extractelement <4 x float> %153, i32 3
- %158 = fmul float %26, 0x3F45A07B40000000
- %159 = fmul float %27, 0x3F45A07B40000000
- %160 = fmul float %28, 0x3F45A07B40000000
- %161 = insertelement <4 x float> undef, float %158, i32 0
- %162 = insertelement <4 x float> %161, float %159, i32 1
- %163 = insertelement <4 x float> %162, float %160, i32 2
- %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3
- %165 = extractelement <4 x float> %164, i32 0
- %166 = extractelement <4 x float> %164, i32 1
- %167 = extractelement <4 x float> %164, i32 2
- %168 = extractelement <4 x float> %164, i32 3
- %169 = insertelement <4 x float> undef, float %165, i32 0
- %170 = insertelement <4 x float> %169, float %166, i32 1
- %171 = insertelement <4 x float> %170, float %167, i32 2
- %172 = insertelement <4 x float> %171, float %168, i32 3
- %173 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %172, i32 16, i32 0, i32 3)
- %174 = extractelement <4 x float> %173, i32 0
- %175 = extractelement <4 x float> %173, i32 1
- %176 = extractelement <4 x float> %173, i32 2
- %177 = extractelement <4 x float> %173, i32 3
- %178 = fmul float %176, 3.000000e+03
- %179 = fadd float %178, %28
- %180 = fdiv float 1.000000e+00, %33
- %181 = fmul float %32, %180
- %182 = call float @fabs(float %181)
- %183 = fmul float %174, 0x3FD99999A0000000
- %184 = fadd float %183, 0x3FAEB851E0000000
- %185 = fmul float %175, 0x3FE3333340000000
- %186 = fadd float %185, %184
- %187 = fmul float %176, 2.000000e+00
- %188 = fadd float %187, %186
- %189 = fmul float %177, 4.000000e+00
- %190 = fadd float %189, %188
- %191 = fmul float %154, 0x3FB99999A0000000
- %192 = fadd float %191, %190
- %193 = fmul float %155, 0x3FD99999A0000000
- %194 = fadd float %193, %192
- %195 = fmul float %156, 0x3FE99999A0000000
- %196 = fadd float %195, %194
- %197 = fmul float %157, 0x4000CCCCC0000000
- %198 = fadd float %197, %196
- %199 = fmul float 0xBE5EFB4CC0000000, %182
- %200 = fmul float %199, %182
- %201 = call float @llvm.AMDIL.exp.(float %200)
- %202 = call float @llvm.AMDGPU.lrp(float %201, float %198, float 0x3FA99999A0000000)
- %203 = fadd float %202, 0x3FF4CCCCC0000000
- %204 = fmul float %203, 0x3FE1C71C80000000
- %205 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00)
- %206 = fadd float %202, 0x3FF4CCCCC0000000
- %207 = fmul float %206, 0x3FE1C71C80000000
- %208 = call float @llvm.AMDIL.clamp.(float %207, float 0.000000e+00, float 1.000000e+00)
- %209 = fadd float %202, 2.000000e+00
- %210 = fmul float %209, 0x3FD611A7A0000000
- %211 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00)
- %212 = fmul float 2.000000e+00, %205
- %213 = fsub float -0.000000e+00, %212
- %214 = fadd float 3.000000e+00, %213
- %215 = fmul float %205, %214
- %216 = fmul float %205, %215
- %217 = fmul float 2.000000e+00, %208
- %218 = fsub float -0.000000e+00, %217
- %219 = fadd float 3.000000e+00, %218
- %220 = fmul float %208, %219
- %221 = fmul float %208, %220
- %222 = fmul float 2.000000e+00, %211
- %223 = fsub float -0.000000e+00, %222
- %224 = fadd float 3.000000e+00, %223
- %225 = fmul float %211, %224
- %226 = fmul float %211, %225
- %227 = fmul float %26, 0x3F368B5CC0000000
- %228 = fmul float %27, 0x3F368B5CC0000000
- %229 = insertelement <4 x float> undef, float %227, i32 0
- %230 = insertelement <4 x float> %229, float %228, i32 1
- %231 = insertelement <4 x float> %230, float 0.000000e+00, i32 2
- %232 = insertelement <4 x float> %231, float 0.000000e+00, i32 3
- %233 = extractelement <4 x float> %232, i32 0
- %234 = extractelement <4 x float> %232, i32 1
- %235 = insertelement <4 x float> undef, float %233, i32 0
- %236 = insertelement <4 x float> %235, float %234, i32 1
- %237 = insertelement <4 x float> %236, float undef, i32 2
- %238 = insertelement <4 x float> %237, float undef, i32 3
- %239 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %238, i32 17, i32 1, i32 2)
- %240 = extractelement <4 x float> %239, i32 0
- %241 = insertelement <4 x float> undef, float %240, i32 0
- %242 = insertelement <4 x float> %241, float %228, i32 1
- %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 2
- %244 = insertelement <4 x float> %243, float 0.000000e+00, i32 3
- %245 = extractelement <4 x float> %244, i32 0
- %246 = insertelement <4 x float> undef, float %245, i32 0
- %247 = insertelement <4 x float> %246, float undef, i32 1
- %248 = insertelement <4 x float> %247, float undef, i32 2
- %249 = insertelement <4 x float> %248, float undef, i32 3
- %250 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %249, i32 18, i32 2, i32 1)
- %251 = extractelement <4 x float> %250, i32 0
- %252 = extractelement <4 x float> %250, i32 1
- %253 = extractelement <4 x float> %250, i32 2
- %254 = extractelement <4 x float> %250, i32 3
- %255 = fmul float %251, %216
- %256 = fmul float %252, %221
- %257 = fmul float %253, %226
- %258 = fmul float %254, 0.000000e+00
- %259 = fadd float %202, 0x3FF4CCCCC0000000
- %260 = fmul float %259, 0x3FE1C71C80000000
- %261 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00)
- %262 = fadd float %202, 0x3FF4CCCCC0000000
- %263 = fmul float %262, 0x3FE1C71C80000000
- %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00)
- %265 = fadd float %202, 2.000000e+00
- %266 = fmul float %265, 0x3FD611A7A0000000
- %267 = call float @llvm.AMDIL.clamp.(float %266, float 0.000000e+00, float 1.000000e+00)
- %268 = fmul float 2.000000e+00, %261
- %269 = fsub float -0.000000e+00, %268
- %270 = fadd float 3.000000e+00, %269
- %271 = fmul float %261, %270
- %272 = fmul float %261, %271
- %273 = fmul float 2.000000e+00, %264
- %274 = fsub float -0.000000e+00, %273
- %275 = fadd float 3.000000e+00, %274
- %276 = fmul float %264, %275
- %277 = fmul float %264, %276
- %278 = fmul float 2.000000e+00, %267
- %279 = fsub float -0.000000e+00, %278
- %280 = fadd float 3.000000e+00, %279
- %281 = fmul float %267, %280
- %282 = fmul float %267, %281
- %283 = fmul float %26, 0x3F22DFD6A0000000
- %284 = fmul float %27, 0x3F22DFD6A0000000
- %285 = insertelement <4 x float> undef, float %283, i32 0
- %286 = insertelement <4 x float> %285, float %284, i32 1
- %287 = insertelement <4 x float> %286, float 0.000000e+00, i32 2
- %288 = insertelement <4 x float> %287, float 0.000000e+00, i32 3
- %289 = extractelement <4 x float> %288, i32 0
- %290 = extractelement <4 x float> %288, i32 1
- %291 = insertelement <4 x float> undef, float %289, i32 0
- %292 = insertelement <4 x float> %291, float %290, i32 1
- %293 = insertelement <4 x float> %292, float undef, i32 2
- %294 = insertelement <4 x float> %293, float undef, i32 3
- %295 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %294, i32 19, i32 3, i32 2)
- %296 = extractelement <4 x float> %295, i32 0
- %297 = extractelement <4 x float> %295, i32 1
- %298 = extractelement <4 x float> %295, i32 2
- %299 = extractelement <4 x float> %295, i32 3
- %300 = fmul float %296, %272
- %301 = fmul float %297, %277
- %302 = fmul float %298, %282
- %303 = fmul float %299, 0.000000e+00
- %304 = fmul float %temp68.1, %37
- %305 = fmul float %temp68.1, %38
- %306 = fmul float %temp68.1, %39
- %307 = fmul float %temp69.0, %40
- %308 = fadd float %307, %304
- %309 = fmul float %temp69.0, %41
- %310 = fadd float %309, %305
- %311 = fmul float %temp69.0, %42
- %312 = fadd float %311, %306
- %313 = fmul float %temp70.0, %34
- %314 = fadd float %313, %308
- %315 = fmul float %temp70.0, %35
- %316 = fadd float %315, %310
- %317 = fmul float %temp70.0, %36
- %318 = fadd float %317, %312
- %319 = insertelement <4 x float> undef, float %314, i32 0
- %320 = insertelement <4 x float> %319, float %316, i32 1
- %321 = insertelement <4 x float> %320, float %318, i32 2
- %322 = insertelement <4 x float> %321, float 0.000000e+00, i32 3
- %323 = insertelement <4 x float> undef, float %314, i32 0
- %324 = insertelement <4 x float> %323, float %316, i32 1
- %325 = insertelement <4 x float> %324, float %318, i32 2
- %326 = insertelement <4 x float> %325, float 0.000000e+00, i32 3
- %327 = call float @llvm.AMDGPU.dp4(<4 x float> %322, <4 x float> %326)
- %328 = call float @llvm.AMDGPU.rsq.f32(float %327)
- %329 = fmul float %314, %328
- %330 = fmul float %316, %328
- %331 = fmul float %318, %328
- %332 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
- %333 = extractelement <4 x float> %332, i32 0
- %334 = fsub float -0.000000e+00, %333
- %335 = fadd float 1.000000e+00, %334
- %336 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %337 = extractelement <4 x float> %336, i32 0
- %338 = fsub float -0.000000e+00, %337
- %339 = fadd float 1.000000e+00, %338
- %340 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %341 = extractelement <4 x float> %340, i32 0
- %342 = fsub float -0.000000e+00, %341
- %343 = fadd float 1.000000e+00, %342
- %344 = fsub float -0.000000e+00, %335
- %345 = fadd float %202, %344
- %346 = fsub float -0.000000e+00, %339
- %347 = fadd float %202, %346
- %348 = fadd float %347, 0xBFE3333340000000
- %349 = fsub float -0.000000e+00, %202
- %350 = fsub float -0.000000e+00, %343
- %351 = fadd float %349, %350
- %352 = insertelement <4 x float> undef, float %43, i32 0
- %353 = insertelement <4 x float> %352, float %44, i32 1
- %354 = insertelement <4 x float> %353, float %45, i32 2
- %355 = insertelement <4 x float> %354, float 0.000000e+00, i32 3
- %356 = insertelement <4 x float> undef, float %43, i32 0
- %357 = insertelement <4 x float> %356, float %44, i32 1
- %358 = insertelement <4 x float> %357, float %45, i32 2
- %359 = insertelement <4 x float> %358, float 0.000000e+00, i32 3
- %360 = call float @llvm.AMDGPU.dp4(<4 x float> %355, <4 x float> %359)
- %361 = call float @llvm.AMDGPU.rsq.f32(float %360)
- %362 = fmul float %45, %361
- %363 = call float @fabs(float %362)
- %364 = fmul float %176, 0x3FECCCCCC0000000
- %365 = fadd float %364, %363
- %366 = fadd float %365, 0xBFEFAE1480000000
- %367 = fmul float %366, 0xC023FFFFC0000000
- %368 = call float @llvm.AMDIL.clamp.(float %367, float 0.000000e+00, float 1.000000e+00)
- %369 = fsub float -0.000000e+00, %335
- %370 = fadd float %202, %369
- %371 = fadd float %370, 0x3FBEB851E0000000
- %372 = fsub float -0.000000e+00, %339
- %373 = fadd float %202, %372
- %374 = fadd float %373, 0xBFE0A3D700000000
- %375 = fsub float -0.000000e+00, %202
- %376 = fsub float -0.000000e+00, %343
- %377 = fadd float %375, %376
- %378 = insertelement <4 x float> undef, float %43, i32 0
- %379 = insertelement <4 x float> %378, float %44, i32 1
- %380 = insertelement <4 x float> %379, float %45, i32 2
- %381 = insertelement <4 x float> %380, float 0.000000e+00, i32 3
- %382 = insertelement <4 x float> undef, float %43, i32 0
- %383 = insertelement <4 x float> %382, float %44, i32 1
- %384 = insertelement <4 x float> %383, float %45, i32 2
- %385 = insertelement <4 x float> %384, float 0.000000e+00, i32 3
- %386 = call float @llvm.AMDGPU.dp4(<4 x float> %381, <4 x float> %385)
- %387 = call float @llvm.AMDGPU.rsq.f32(float %386)
- %388 = fmul float %45, %387
- %389 = call float @fabs(float %388)
- %390 = fmul float %176, 0x3FF51EB860000000
- %391 = fadd float %390, %389
- %392 = fadd float %391, 0xBFEFAE1480000000
- %393 = fmul float %392, 0xC0490001A0000000
- %394 = call float @llvm.AMDIL.clamp.(float %393, float 0.000000e+00, float 1.000000e+00)
- %395 = fmul float 2.000000e+00, %368
- %396 = fsub float -0.000000e+00, %395
- %397 = fadd float 3.000000e+00, %396
- %398 = fmul float %368, %397
- %399 = fmul float %368, %398
- %400 = call float @llvm.AMDGPU.lrp(float %399, float %255, float %345)
- %401 = call float @llvm.AMDGPU.lrp(float %399, float %256, float %348)
- %402 = call float @llvm.AMDGPU.lrp(float %399, float %257, float %351)
- %403 = call float @llvm.AMDGPU.lrp(float %399, float %258, float 0.000000e+00)
- %404 = fmul float 2.000000e+00, %394
- %405 = fsub float -0.000000e+00, %404
- %406 = fadd float 3.000000e+00, %405
- %407 = fmul float %394, %406
- %408 = fmul float %394, %407
- %409 = call float @llvm.AMDGPU.lrp(float %408, float %255, float %371)
- %410 = call float @llvm.AMDGPU.lrp(float %408, float %256, float %374)
- %411 = call float @llvm.AMDGPU.lrp(float %408, float %257, float %377)
- %412 = call float @llvm.AMDGPU.lrp(float %408, float %258, float 0x3FD3333340000000)
- %413 = fcmp oge float 2.200000e+03, %179
- %414 = sext i1 %413 to i32
- %415 = bitcast i32 %414 to float
- %416 = bitcast float %415 to i32
- %417 = icmp ne i32 %416, 0
- br i1 %417, label %IF161, label %ENDIF160
-
-LOOP: ; preds = %ENDIF139, %IF137
- %temp88.0 = phi float [ 0.000000e+00, %IF137 ], [ %446, %ENDIF139 ]
- %temp92.0 = phi float [ 1.000000e+00, %IF137 ], [ %.temp92.0, %ENDIF139 ]
- %temp96.0 = phi float [ 0.000000e+00, %IF137 ], [ %477, %ENDIF139 ]
- %418 = bitcast float %temp96.0 to i32
- %419 = icmp sge i32 %418, %137
- %420 = sext i1 %419 to i32
- %421 = bitcast i32 %420 to float
- %422 = bitcast float %421 to i32
- %423 = icmp ne i32 %422, 0
- br i1 %423, label %IF140, label %ENDIF139
-
-IF140: ; preds = %LOOP
- %424 = fmul float %133, 5.000000e-01
- %425 = fmul float %129, %temp92.0
- %426 = fadd float %425, %22
- %427 = fmul float %130, %temp92.0
- %428 = fadd float %427, %23
- %429 = insertelement <4 x float> undef, float %426, i32 0
- %430 = insertelement <4 x float> %429, float %428, i32 1
- %431 = insertelement <4 x float> %430, float 0.000000e+00, i32 2
- %432 = insertelement <4 x float> %431, float 0.000000e+00, i32 3
- %433 = extractelement <4 x float> %432, i32 0
- %434 = extractelement <4 x float> %432, i32 1
- %435 = insertelement <4 x float> undef, float %433, i32 0
- %436 = insertelement <4 x float> %435, float %434, i32 1
- %437 = insertelement <4 x float> %436, float undef, i32 2
- %438 = insertelement <4 x float> %437, float undef, i32 3
- %439 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %438, i32 20, i32 4, i32 2)
- %440 = extractelement <4 x float> %439, i32 3
- %441 = fcmp oge float %temp92.0, %440
- %442 = sext i1 %441 to i32
- %443 = bitcast i32 %442 to float
- %444 = bitcast float %443 to i32
- %445 = icmp ne i32 %444, 0
- br i1 %445, label %IF146, label %ENDIF145
-
-ENDIF139: ; preds = %LOOP
- %446 = fadd float %temp88.0, %133
- %447 = fmul float %129, %446
- %448 = fadd float %447, %22
- %449 = fmul float %130, %446
- %450 = fadd float %449, %23
- %451 = insertelement <4 x float> undef, float %448, i32 0
- %452 = insertelement <4 x float> %451, float %450, i32 1
- %453 = insertelement <4 x float> %452, float 0.000000e+00, i32 2
- %454 = insertelement <4 x float> %453, float 0.000000e+00, i32 3
- %455 = extractelement <4 x float> %454, i32 0
- %456 = extractelement <4 x float> %454, i32 1
- %457 = insertelement <4 x float> undef, float %455, i32 0
- %458 = insertelement <4 x float> %457, float %456, i32 1
- %459 = insertelement <4 x float> %458, float undef, i32 2
- %460 = insertelement <4 x float> %459, float undef, i32 3
- %461 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %460, i32 20, i32 4, i32 2)
- %462 = extractelement <4 x float> %461, i32 3
- %463 = fcmp olt float 0x3FEFDF3B60000000, %temp92.0
- %464 = sext i1 %463 to i32
- %465 = bitcast i32 %464 to float
- %466 = fcmp oge float %446, %462
- %467 = sext i1 %466 to i32
- %468 = bitcast i32 %467 to float
- %469 = bitcast float %465 to i32
- %470 = bitcast float %468 to i32
- %471 = and i32 %469, %470
- %472 = bitcast i32 %471 to float
- %473 = bitcast float %472 to i32
- %474 = icmp ne i32 %473, 0
- %.temp92.0 = select i1 %474, float %446, float %temp92.0
- %475 = bitcast float %temp96.0 to i32
- %476 = add i32 %475, 1
- %477 = bitcast i32 %476 to float
- br label %LOOP
-
-IF146: ; preds = %IF140
- %478 = fmul float 2.000000e+00, %424
- %479 = fsub float -0.000000e+00, %478
- %480 = fadd float %temp92.0, %479
- br label %ENDIF145
-
-ENDIF145: ; preds = %IF140, %IF146
- %temp88.1 = phi float [ %480, %IF146 ], [ %temp92.0, %IF140 ]
- %481 = fadd float %temp88.1, %424
- %482 = fmul float %424, 5.000000e-01
- %483 = fmul float %129, %481
- %484 = fadd float %483, %22
- %485 = fmul float %130, %481
- %486 = fadd float %485, %23
- %487 = insertelement <4 x float> undef, float %484, i32 0
- %488 = insertelement <4 x float> %487, float %486, i32 1
- %489 = insertelement <4 x float> %488, float 0.000000e+00, i32 2
- %490 = insertelement <4 x float> %489, float %440, i32 3
- %491 = extractelement <4 x float> %490, i32 0
- %492 = extractelement <4 x float> %490, i32 1
- %493 = insertelement <4 x float> undef, float %491, i32 0
- %494 = insertelement <4 x float> %493, float %492, i32 1
- %495 = insertelement <4 x float> %494, float undef, i32 2
- %496 = insertelement <4 x float> %495, float undef, i32 3
- %497 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %496, i32 20, i32 4, i32 2)
- %498 = extractelement <4 x float> %497, i32 3
- %499 = fcmp oge float %481, %498
- %500 = sext i1 %499 to i32
- %501 = bitcast i32 %500 to float
- %502 = bitcast float %501 to i32
- %503 = icmp ne i32 %502, 0
- br i1 %503, label %IF149, label %ENDIF148
-
-IF149: ; preds = %ENDIF145
- %504 = fmul float 2.000000e+00, %482
- %505 = fsub float -0.000000e+00, %504
- %506 = fadd float %481, %505
- br label %ENDIF148
-
-ENDIF148: ; preds = %ENDIF145, %IF149
- %temp88.2 = phi float [ %506, %IF149 ], [ %481, %ENDIF145 ]
- %temp92.2 = phi float [ %481, %IF149 ], [ %temp92.0, %ENDIF145 ]
- %507 = fadd float %temp88.2, %482
- %508 = fmul float %482, 5.000000e-01
- %509 = fmul float %129, %507
- %510 = fadd float %509, %22
- %511 = fmul float %130, %507
- %512 = fadd float %511, %23
- %513 = insertelement <4 x float> undef, float %510, i32 0
- %514 = insertelement <4 x float> %513, float %512, i32 1
- %515 = insertelement <4 x float> %514, float 0.000000e+00, i32 2
- %516 = insertelement <4 x float> %515, float %498, i32 3
- %517 = extractelement <4 x float> %516, i32 0
- %518 = extractelement <4 x float> %516, i32 1
- %519 = insertelement <4 x float> undef, float %517, i32 0
- %520 = insertelement <4 x float> %519, float %518, i32 1
- %521 = insertelement <4 x float> %520, float undef, i32 2
- %522 = insertelement <4 x float> %521, float undef, i32 3
- %523 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %522, i32 20, i32 4, i32 2)
- %524 = extractelement <4 x float> %523, i32 3
- %525 = fcmp oge float %507, %524
- %526 = sext i1 %525 to i32
- %527 = bitcast i32 %526 to float
- %528 = bitcast float %527 to i32
- %529 = icmp ne i32 %528, 0
- br i1 %529, label %IF152, label %ENDIF151
-
-IF152: ; preds = %ENDIF148
- %530 = fmul float 2.000000e+00, %508
- %531 = fsub float -0.000000e+00, %530
- %532 = fadd float %507, %531
- br label %ENDIF151
-
-ENDIF151: ; preds = %ENDIF148, %IF152
- %temp88.3 = phi float [ %532, %IF152 ], [ %507, %ENDIF148 ]
- %temp92.3 = phi float [ %507, %IF152 ], [ %temp92.2, %ENDIF148 ]
- %533 = fadd float %temp88.3, %508
- %534 = fmul float %508, 5.000000e-01
- %535 = fmul float %129, %533
- %536 = fadd float %535, %22
- %537 = fmul float %130, %533
- %538 = fadd float %537, %23
- %539 = insertelement <4 x float> undef, float %536, i32 0
- %540 = insertelement <4 x float> %539, float %538, i32 1
- %541 = insertelement <4 x float> %540, float 0.000000e+00, i32 2
- %542 = insertelement <4 x float> %541, float %524, i32 3
- %543 = extractelement <4 x float> %542, i32 0
- %544 = extractelement <4 x float> %542, i32 1
- %545 = insertelement <4 x float> undef, float %543, i32 0
- %546 = insertelement <4 x float> %545, float %544, i32 1
- %547 = insertelement <4 x float> %546, float undef, i32 2
- %548 = insertelement <4 x float> %547, float undef, i32 3
- %549 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %548, i32 20, i32 4, i32 2)
- %550 = extractelement <4 x float> %549, i32 3
- %551 = fcmp oge float %533, %550
- %552 = sext i1 %551 to i32
- %553 = bitcast i32 %552 to float
- %554 = bitcast float %553 to i32
- %555 = icmp ne i32 %554, 0
- br i1 %555, label %IF155, label %ENDIF154
-
-IF155: ; preds = %ENDIF151
- %556 = fmul float 2.000000e+00, %534
- %557 = fsub float -0.000000e+00, %556
- %558 = fadd float %533, %557
- br label %ENDIF154
-
-ENDIF154: ; preds = %ENDIF151, %IF155
- %temp88.4 = phi float [ %558, %IF155 ], [ %533, %ENDIF151 ]
- %temp92.4 = phi float [ %533, %IF155 ], [ %temp92.3, %ENDIF151 ]
- %559 = fadd float %temp88.4, %534
- %560 = fmul float %129, %559
- %561 = fadd float %560, %22
- %562 = fmul float %130, %559
- %563 = fadd float %562, %23
- %564 = insertelement <4 x float> undef, float %561, i32 0
- %565 = insertelement <4 x float> %564, float %563, i32 1
- %566 = insertelement <4 x float> %565, float 0.000000e+00, i32 2
- %567 = insertelement <4 x float> %566, float %550, i32 3
- %568 = extractelement <4 x float> %567, i32 0
- %569 = extractelement <4 x float> %567, i32 1
- %570 = insertelement <4 x float> undef, float %568, i32 0
- %571 = insertelement <4 x float> %570, float %569, i32 1
- %572 = insertelement <4 x float> %571, float undef, i32 2
- %573 = insertelement <4 x float> %572, float undef, i32 3
- %574 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %573, i32 20, i32 4, i32 2)
- %575 = extractelement <4 x float> %574, i32 3
- %576 = fcmp oge float %559, %575
- %577 = sext i1 %576 to i32
- %578 = bitcast i32 %577 to float
- %579 = bitcast float %578 to i32
- %580 = icmp ne i32 %579, 0
- %.temp92.4 = select i1 %580, float %559, float %temp92.4
- %581 = fmul float %129, %.temp92.4
- %582 = fadd float %581, %22
- %583 = fmul float %130, %.temp92.4
- %584 = fadd float %583, %23
- %585 = insertelement <4 x float> undef, float %582, i32 0
- %586 = insertelement <4 x float> %585, float %584, i32 1
- %587 = insertelement <4 x float> %586, float 0.000000e+00, i32 2
- %588 = insertelement <4 x float> %587, float %575, i32 3
- %589 = extractelement <4 x float> %588, i32 0
- %590 = extractelement <4 x float> %588, i32 1
- %591 = insertelement <4 x float> undef, float %589, i32 0
- %592 = insertelement <4 x float> %591, float %590, i32 1
- %593 = insertelement <4 x float> %592, float undef, i32 2
- %594 = insertelement <4 x float> %593, float undef, i32 3
- %595 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %594, i32 20, i32 4, i32 2)
- %596 = extractelement <4 x float> %595, i32 0
- %597 = extractelement <4 x float> %595, i32 1
- %598 = extractelement <4 x float> %595, i32 2
- %599 = fmul float %596, 2.000000e+00
- %600 = fadd float %599, -1.000000e+00
- %601 = fmul float %597, 2.000000e+00
- %602 = fadd float %601, -1.000000e+00
- %603 = fmul float %598, 2.000000e+00
- %604 = fadd float %603, -1.000000e+00
- br label %ENDIF136
-
-IF161: ; preds = %ENDIF136
- %605 = fmul float %202, 0x3FB99999A0000000
- %606 = fcmp uge float 0x3FE4CCCCC0000000, %605
- %607 = select i1 %606, float 0x3FE4CCCCC0000000, float %605
- %608 = fcmp uge float %607, 5.000000e-01
- %609 = select i1 %608, float 5.000000e-01, float %607
- %610 = call float @llvm.AMDGPU.lrp(float %609, float %400, float %300)
- %611 = call float @llvm.AMDGPU.lrp(float %609, float %401, float %301)
- %612 = call float @llvm.AMDGPU.lrp(float %609, float %402, float %302)
- %613 = call float @llvm.AMDGPU.lrp(float %609, float %403, float %303)
- %614 = insertelement <4 x float> undef, float %329, i32 0
- %615 = insertelement <4 x float> %614, float %330, i32 1
- %616 = insertelement <4 x float> %615, float %331, i32 2
- %617 = insertelement <4 x float> %616, float 0.000000e+00, i32 3
- %618 = insertelement <4 x float> undef, float %63, i32 0
- %619 = insertelement <4 x float> %618, float %65, i32 1
- %620 = insertelement <4 x float> %619, float %67, i32 2
- %621 = insertelement <4 x float> %620, float 0.000000e+00, i32 3
- %622 = call float @llvm.AMDGPU.dp4(<4 x float> %617, <4 x float> %621)
- %623 = fcmp uge float 0x3FE6666660000000, %622
- %624 = select i1 %623, float 0x3FE6666660000000, float %622
- %625 = fmul float %8, %624
- %626 = fmul float %13, %624
- %627 = fmul float %18, %624
- %628 = insertelement <4 x float> undef, float %34, i32 0
- %629 = insertelement <4 x float> %628, float %35, i32 1
- %630 = insertelement <4 x float> %629, float %36, i32 2
- %631 = insertelement <4 x float> %630, float 0.000000e+00, i32 3
- %632 = insertelement <4 x float> undef, float %63, i32 0
- %633 = insertelement <4 x float> %632, float %65, i32 1
- %634 = insertelement <4 x float> %633, float %67, i32 2
- %635 = insertelement <4 x float> %634, float 0.000000e+00, i32 3
- %636 = call float @llvm.AMDGPU.dp4(<4 x float> %631, <4 x float> %635)
- %637 = fcmp uge float 0x3FECCCCCC0000000, %636
- %638 = select i1 %637, float 0x3FECCCCCC0000000, float %636
- %639 = fmul float %625, %638
- %640 = fmul float %626, %638
- %641 = fmul float %627, %638
- br label %ENDIF160
-
-ENDIF160: ; preds = %ENDIF136, %IF161
- %temp84.0 = phi float [ %610, %IF161 ], [ %255, %ENDIF136 ]
- %temp85.0 = phi float [ %611, %IF161 ], [ %256, %ENDIF136 ]
- %temp86.0 = phi float [ %612, %IF161 ], [ %257, %ENDIF136 ]
- %temp87.0 = phi float [ %613, %IF161 ], [ %258, %ENDIF136 ]
- %temp92.6 = phi float [ %639, %IF161 ], [ %415, %ENDIF136 ]
- %temp93.0 = phi float [ %640, %IF161 ], [ 0.000000e+00, %ENDIF136 ]
- %temp94.0 = phi float [ %641, %IF161 ], [ 0.000000e+00, %ENDIF136 ]
- %642 = fcmp olt float 2.200000e+03, %179
- %643 = sext i1 %642 to i32
- %644 = bitcast i32 %643 to float
- %645 = fcmp olt float %179, 2.300000e+03
- %646 = sext i1 %645 to i32
- %647 = bitcast i32 %646 to float
- %648 = bitcast float %644 to i32
- %649 = bitcast float %647 to i32
- %650 = and i32 %648, %649
- %651 = bitcast i32 %650 to float
- %652 = bitcast float %651 to i32
- %653 = icmp ne i32 %652, 0
- br i1 %653, label %IF164, label %ENDIF163
-
-IF164: ; preds = %ENDIF160
- %654 = fmul float %202, 5.000000e-01
- %655 = fcmp uge float 0x3FE4CCCCC0000000, %654
- %656 = select i1 %655, float 0x3FE4CCCCC0000000, float %654
- %657 = fcmp uge float %656, 0x3FD6666660000000
- %658 = select i1 %657, float 0x3FD6666660000000, float %656
- %659 = call float @llvm.AMDGPU.lrp(float %658, float %400, float %300)
- %660 = call float @llvm.AMDGPU.lrp(float %658, float %401, float %301)
- %661 = call float @llvm.AMDGPU.lrp(float %658, float %402, float %302)
- %662 = call float @llvm.AMDGPU.lrp(float %658, float %403, float %303)
- %663 = insertelement <4 x float> undef, float %329, i32 0
- %664 = insertelement <4 x float> %663, float %330, i32 1
- %665 = insertelement <4 x float> %664, float %331, i32 2
- %666 = insertelement <4 x float> %665, float 0.000000e+00, i32 3
- %667 = insertelement <4 x float> undef, float %63, i32 0
- %668 = insertelement <4 x float> %667, float %65, i32 1
- %669 = insertelement <4 x float> %668, float %67, i32 2
- %670 = insertelement <4 x float> %669, float 0.000000e+00, i32 3
- %671 = call float @llvm.AMDGPU.dp4(<4 x float> %666, <4 x float> %670)
- %672 = fcmp uge float 0x3FE6666660000000, %671
- %673 = select i1 %672, float 0x3FE6666660000000, float %671
- %674 = fmul float %8, %673
- %675 = fmul float %13, %673
- %676 = fmul float %18, %673
- %677 = insertelement <4 x float> undef, float %34, i32 0
- %678 = insertelement <4 x float> %677, float %35, i32 1
- %679 = insertelement <4 x float> %678, float %36, i32 2
- %680 = insertelement <4 x float> %679, float 0.000000e+00, i32 3
- %681 = insertelement <4 x float> undef, float %63, i32 0
- %682 = insertelement <4 x float> %681, float %65, i32 1
- %683 = insertelement <4 x float> %682, float %67, i32 2
- %684 = insertelement <4 x float> %683, float 0.000000e+00, i32 3
- %685 = call float @llvm.AMDGPU.dp4(<4 x float> %680, <4 x float> %684)
- %686 = fcmp uge float 0x3FECCCCCC0000000, %685
- %687 = select i1 %686, float 0x3FECCCCCC0000000, float %685
- %688 = fmul float %674, %687
- %689 = fmul float %675, %687
- %690 = fmul float %676, %687
- br label %ENDIF163
-
-ENDIF163: ; preds = %ENDIF160, %IF164
- %temp84.1 = phi float [ %659, %IF164 ], [ %temp84.0, %ENDIF160 ]
- %temp85.1 = phi float [ %660, %IF164 ], [ %temp85.0, %ENDIF160 ]
- %temp86.1 = phi float [ %661, %IF164 ], [ %temp86.0, %ENDIF160 ]
- %temp87.1 = phi float [ %662, %IF164 ], [ %temp87.0, %ENDIF160 ]
- %temp92.7 = phi float [ %688, %IF164 ], [ %temp92.6, %ENDIF160 ]
- %temp93.1 = phi float [ %689, %IF164 ], [ %temp93.0, %ENDIF160 ]
- %temp94.1 = phi float [ %690, %IF164 ], [ %temp94.0, %ENDIF160 ]
- %691 = fcmp oge float %179, 2.300000e+03
- %692 = sext i1 %691 to i32
- %693 = bitcast i32 %692 to float
- %694 = fcmp olt float %179, 2.480000e+03
- %695 = sext i1 %694 to i32
- %696 = bitcast i32 %695 to float
- %697 = bitcast float %693 to i32
- %698 = bitcast float %696 to i32
- %699 = and i32 %697, %698
- %700 = bitcast i32 %699 to float
- %701 = bitcast float %700 to i32
- %702 = icmp ne i32 %701, 0
- br i1 %702, label %IF167, label %ENDIF166
-
-IF167: ; preds = %ENDIF163
- %703 = fmul float %202, 5.000000e-01
- %704 = fcmp uge float 0x3FE4CCCCC0000000, %703
- %705 = select i1 %704, float 0x3FE4CCCCC0000000, float %703
- %706 = fcmp uge float %705, 0x3FD3333340000000
- %707 = select i1 %706, float 0x3FD3333340000000, float %705
- %708 = call float @llvm.AMDGPU.lrp(float %707, float %409, float %300)
- %709 = call float @llvm.AMDGPU.lrp(float %707, float %410, float %301)
- %710 = call float @llvm.AMDGPU.lrp(float %707, float %411, float %302)
- %711 = call float @llvm.AMDGPU.lrp(float %707, float %412, float %303)
- %712 = insertelement <4 x float> undef, float %329, i32 0
- %713 = insertelement <4 x float> %712, float %330, i32 1
- %714 = insertelement <4 x float> %713, float %331, i32 2
- %715 = insertelement <4 x float> %714, float 0.000000e+00, i32 3
- %716 = insertelement <4 x float> undef, float %63, i32 0
- %717 = insertelement <4 x float> %716, float %65, i32 1
- %718 = insertelement <4 x float> %717, float %67, i32 2
- %719 = insertelement <4 x float> %718, float 0.000000e+00, i32 3
- %720 = call float @llvm.AMDGPU.dp4(<4 x float> %715, <4 x float> %719)
- %721 = fcmp uge float 0x3FEB333340000000, %720
- %722 = select i1 %721, float 0x3FEB333340000000, float %720
- %723 = fmul float %8, %722
- %724 = fmul float %13, %722
- %725 = fmul float %18, %722
- %726 = insertelement <4 x float> undef, float %34, i32 0
- %727 = insertelement <4 x float> %726, float %35, i32 1
- %728 = insertelement <4 x float> %727, float %36, i32 2
- %729 = insertelement <4 x float> %728, float 0.000000e+00, i32 3
- %730 = insertelement <4 x float> undef, float %63, i32 0
- %731 = insertelement <4 x float> %730, float %65, i32 1
- %732 = insertelement <4 x float> %731, float %67, i32 2
- %733 = insertelement <4 x float> %732, float 0.000000e+00, i32 3
- %734 = call float @llvm.AMDGPU.dp4(<4 x float> %729, <4 x float> %733)
- %735 = fcmp uge float 0x3FECCCCCC0000000, %734
- %736 = select i1 %735, float 0x3FECCCCCC0000000, float %734
- %737 = fmul float %723, %736
- %738 = fmul float %724, %736
- %739 = fmul float %725, %736
- br label %ENDIF166
-
-ENDIF166: ; preds = %ENDIF163, %IF167
- %temp84.2 = phi float [ %708, %IF167 ], [ %temp84.1, %ENDIF163 ]
- %temp85.2 = phi float [ %709, %IF167 ], [ %temp85.1, %ENDIF163 ]
- %temp86.2 = phi float [ %710, %IF167 ], [ %temp86.1, %ENDIF163 ]
- %temp87.2 = phi float [ %711, %IF167 ], [ %temp87.1, %ENDIF163 ]
- %temp92.8 = phi float [ %737, %IF167 ], [ %temp92.7, %ENDIF163 ]
- %temp93.2 = phi float [ %738, %IF167 ], [ %temp93.1, %ENDIF163 ]
- %temp94.2 = phi float [ %739, %IF167 ], [ %temp94.1, %ENDIF163 ]
- %740 = fcmp oge float %179, 2.480000e+03
- %741 = sext i1 %740 to i32
- %742 = bitcast i32 %741 to float
- %743 = fcmp olt float %179, 2.530000e+03
- %744 = sext i1 %743 to i32
- %745 = bitcast i32 %744 to float
- %746 = bitcast float %742 to i32
- %747 = bitcast float %745 to i32
- %748 = and i32 %746, %747
- %749 = bitcast i32 %748 to float
- %750 = bitcast float %749 to i32
- %751 = icmp ne i32 %750, 0
- br i1 %751, label %IF170, label %ENDIF169
-
-IF170: ; preds = %ENDIF166
- %752 = fmul float %202, 5.000000e-01
- %753 = fcmp uge float 0x3FE4CCCCC0000000, %752
- %754 = select i1 %753, float 0x3FE4CCCCC0000000, float %752
- %755 = fcmp uge float %754, 0x3FC99999A0000000
- %756 = select i1 %755, float 0x3FC99999A0000000, float %754
- %757 = call float @llvm.AMDGPU.lrp(float %756, float %409, float %300)
- %758 = call float @llvm.AMDGPU.lrp(float %756, float %410, float %301)
- %759 = call float @llvm.AMDGPU.lrp(float %756, float %411, float %302)
- %760 = call float @llvm.AMDGPU.lrp(float %756, float %412, float %303)
- %761 = insertelement <4 x float> undef, float %329, i32 0
- %762 = insertelement <4 x float> %761, float %330, i32 1
- %763 = insertelement <4 x float> %762, float %331, i32 2
- %764 = insertelement <4 x float> %763, float 0.000000e+00, i32 3
- %765 = insertelement <4 x float> undef, float %63, i32 0
- %766 = insertelement <4 x float> %765, float %65, i32 1
- %767 = insertelement <4 x float> %766, float %67, i32 2
- %768 = insertelement <4 x float> %767, float 0.000000e+00, i32 3
- %769 = call float @llvm.AMDGPU.dp4(<4 x float> %764, <4 x float> %768)
- %770 = fcmp uge float 0x3FEB333340000000, %769
- %771 = select i1 %770, float 0x3FEB333340000000, float %769
- %772 = fmul float %8, %771
- %773 = fmul float %13, %771
- %774 = fmul float %18, %771
- %775 = insertelement <4 x float> undef, float %34, i32 0
- %776 = insertelement <4 x float> %775, float %35, i32 1
- %777 = insertelement <4 x float> %776, float %36, i32 2
- %778 = insertelement <4 x float> %777, float 0.000000e+00, i32 3
- %779 = insertelement <4 x float> undef, float %63, i32 0
- %780 = insertelement <4 x float> %779, float %65, i32 1
- %781 = insertelement <4 x float> %780, float %67, i32 2
- %782 = insertelement <4 x float> %781, float 0.000000e+00, i32 3
- %783 = call float @llvm.AMDGPU.dp4(<4 x float> %778, <4 x float> %782)
- %784 = fcmp uge float 0x3FECCCCCC0000000, %783
- %785 = select i1 %784, float 0x3FECCCCCC0000000, float %783
- %786 = fmul float %772, %785
- %787 = fmul float %773, %785
- %788 = fmul float %774, %785
- br label %ENDIF169
-
-ENDIF169: ; preds = %ENDIF166, %IF170
- %temp84.3 = phi float [ %757, %IF170 ], [ %temp84.2, %ENDIF166 ]
- %temp85.3 = phi float [ %758, %IF170 ], [ %temp85.2, %ENDIF166 ]
- %temp86.3 = phi float [ %759, %IF170 ], [ %temp86.2, %ENDIF166 ]
- %temp87.3 = phi float [ %760, %IF170 ], [ %temp87.2, %ENDIF166 ]
- %temp92.9 = phi float [ %786, %IF170 ], [ %temp92.8, %ENDIF166 ]
- %temp93.3 = phi float [ %787, %IF170 ], [ %temp93.2, %ENDIF166 ]
- %temp94.3 = phi float [ %788, %IF170 ], [ %temp94.2, %ENDIF166 ]
- %789 = fcmp oge float %179, 2.530000e+03
- %790 = sext i1 %789 to i32
- %791 = bitcast i32 %790 to float
- %792 = fcmp olt float %179, 2.670000e+03
- %793 = sext i1 %792 to i32
- %794 = bitcast i32 %793 to float
- %795 = bitcast float %791 to i32
- %796 = bitcast float %794 to i32
- %797 = and i32 %795, %796
- %798 = bitcast i32 %797 to float
- %799 = bitcast float %798 to i32
- %800 = icmp ne i32 %799, 0
- br i1 %800, label %IF173, label %ENDIF172
-
-IF173: ; preds = %ENDIF169
- %801 = fmul float %202, 5.000000e-01
- %802 = fcmp uge float 0x3FE4CCCCC0000000, %801
- %803 = select i1 %802, float 0x3FE4CCCCC0000000, float %801
- %804 = fcmp uge float %803, 0x3FB99999A0000000
- %805 = select i1 %804, float 0x3FB99999A0000000, float %803
- %806 = call float @llvm.AMDGPU.lrp(float %805, float %400, float %300)
- %807 = call float @llvm.AMDGPU.lrp(float %805, float %401, float %301)
- %808 = call float @llvm.AMDGPU.lrp(float %805, float %402, float %302)
- %809 = call float @llvm.AMDGPU.lrp(float %805, float %403, float %303)
- %810 = insertelement <4 x float> undef, float %329, i32 0
- %811 = insertelement <4 x float> %810, float %330, i32 1
- %812 = insertelement <4 x float> %811, float %331, i32 2
- %813 = insertelement <4 x float> %812, float 0.000000e+00, i32 3
- %814 = insertelement <4 x float> undef, float %63, i32 0
- %815 = insertelement <4 x float> %814, float %65, i32 1
- %816 = insertelement <4 x float> %815, float %67, i32 2
- %817 = insertelement <4 x float> %816, float 0.000000e+00, i32 3
- %818 = call float @llvm.AMDGPU.dp4(<4 x float> %813, <4 x float> %817)
- %819 = fcmp uge float 0x3FEB333340000000, %818
- %820 = select i1 %819, float 0x3FEB333340000000, float %818
- %821 = fmul float %8, %820
- %822 = fmul float %13, %820
- %823 = fmul float %18, %820
- %824 = insertelement <4 x float> undef, float %34, i32 0
- %825 = insertelement <4 x float> %824, float %35, i32 1
- %826 = insertelement <4 x float> %825, float %36, i32 2
- %827 = insertelement <4 x float> %826, float 0.000000e+00, i32 3
- %828 = insertelement <4 x float> undef, float %63, i32 0
- %829 = insertelement <4 x float> %828, float %65, i32 1
- %830 = insertelement <4 x float> %829, float %67, i32 2
- %831 = insertelement <4 x float> %830, float 0.000000e+00, i32 3
- %832 = call float @llvm.AMDGPU.dp4(<4 x float> %827, <4 x float> %831)
- %833 = fcmp uge float 0x3FECCCCCC0000000, %832
- %834 = select i1 %833, float 0x3FECCCCCC0000000, float %832
- %835 = fmul float %821, %834
- %836 = fmul float %822, %834
- %837 = fmul float %823, %834
- br label %ENDIF172
-
-ENDIF172: ; preds = %ENDIF169, %IF173
- %temp84.4 = phi float [ %806, %IF173 ], [ %temp84.3, %ENDIF169 ]
- %temp85.4 = phi float [ %807, %IF173 ], [ %temp85.3, %ENDIF169 ]
- %temp86.4 = phi float [ %808, %IF173 ], [ %temp86.3, %ENDIF169 ]
- %temp87.4 = phi float [ %809, %IF173 ], [ %temp87.3, %ENDIF169 ]
- %temp92.10 = phi float [ %835, %IF173 ], [ %temp92.9, %ENDIF169 ]
- %temp93.4 = phi float [ %836, %IF173 ], [ %temp93.3, %ENDIF169 ]
- %temp94.4 = phi float [ %837, %IF173 ], [ %temp94.3, %ENDIF169 ]
- %838 = fcmp oge float %179, 2.670000e+03
- %839 = sext i1 %838 to i32
- %840 = bitcast i32 %839 to float
- %841 = bitcast float %840 to i32
- %842 = icmp ne i32 %841, 0
- br i1 %842, label %IF176, label %ENDIF175
-
-IF176: ; preds = %ENDIF172
- %843 = fmul float %202, 0x3FB99999A0000000
- %844 = fcmp uge float 0.000000e+00, %843
- %845 = select i1 %844, float 0.000000e+00, float %843
- %846 = fcmp uge float %845, 0x3FD99999A0000000
- %847 = select i1 %846, float 0x3FD99999A0000000, float %845
- %848 = call float @llvm.AMDGPU.lrp(float %847, float %400, float %300)
- %849 = call float @llvm.AMDGPU.lrp(float %847, float %401, float %301)
- %850 = call float @llvm.AMDGPU.lrp(float %847, float %402, float %302)
- %851 = call float @llvm.AMDGPU.lrp(float %847, float %403, float %303)
- %852 = insertelement <4 x float> undef, float %329, i32 0
- %853 = insertelement <4 x float> %852, float %330, i32 1
- %854 = insertelement <4 x float> %853, float %331, i32 2
- %855 = insertelement <4 x float> %854, float 0.000000e+00, i32 3
- %856 = insertelement <4 x float> undef, float %63, i32 0
- %857 = insertelement <4 x float> %856, float %65, i32 1
- %858 = insertelement <4 x float> %857, float %67, i32 2
- %859 = insertelement <4 x float> %858, float 0.000000e+00, i32 3
- %860 = call float @llvm.AMDGPU.dp4(<4 x float> %855, <4 x float> %859)
- %861 = fcmp uge float 0x3FEB333340000000, %860
- %862 = select i1 %861, float 0x3FEB333340000000, float %860
- %863 = fmul float %8, %862
- %864 = fmul float %13, %862
- %865 = fmul float %18, %862
- %866 = insertelement <4 x float> undef, float %34, i32 0
- %867 = insertelement <4 x float> %866, float %35, i32 1
- %868 = insertelement <4 x float> %867, float %36, i32 2
- %869 = insertelement <4 x float> %868, float 0.000000e+00, i32 3
- %870 = insertelement <4 x float> undef, float %63, i32 0
- %871 = insertelement <4 x float> %870, float %65, i32 1
- %872 = insertelement <4 x float> %871, float %67, i32 2
- %873 = insertelement <4 x float> %872, float 0.000000e+00, i32 3
- %874 = call float @llvm.AMDGPU.dp4(<4 x float> %869, <4 x float> %873)
- %875 = fcmp uge float 0x3FECCCCCC0000000, %874
- %876 = select i1 %875, float 0x3FECCCCCC0000000, float %874
- %877 = fmul float %863, %876
- %878 = fmul float %864, %876
- %879 = fmul float %865, %876
- br label %ENDIF175
-
-ENDIF175: ; preds = %ENDIF172, %IF176
- %temp84.5 = phi float [ %848, %IF176 ], [ %temp84.4, %ENDIF172 ]
- %temp85.5 = phi float [ %849, %IF176 ], [ %temp85.4, %ENDIF172 ]
- %temp86.5 = phi float [ %850, %IF176 ], [ %temp86.4, %ENDIF172 ]
- %temp87.5 = phi float [ %851, %IF176 ], [ %temp87.4, %ENDIF172 ]
- %temp92.11 = phi float [ %877, %IF176 ], [ %temp92.10, %ENDIF172 ]
- %temp93.5 = phi float [ %878, %IF176 ], [ %temp93.4, %ENDIF172 ]
- %temp94.5 = phi float [ %879, %IF176 ], [ %temp94.4, %ENDIF172 ]
- %880 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
- %881 = extractelement <4 x float> %880, i32 0
- %882 = fcmp olt float %881, %179
- %883 = sext i1 %882 to i32
- %884 = bitcast i32 %883 to float
- %885 = bitcast float %884 to i32
- %886 = icmp ne i32 %885, 0
- br i1 %886, label %IF179, label %ENDIF178
-
-IF179: ; preds = %ENDIF175
- %887 = fadd float %202, 1.000000e+00
- %888 = fadd float %202, 1.000000e+00
- %889 = fadd float %202, 1.000000e+00
- %890 = insertelement <4 x float> undef, float %43, i32 0
- %891 = insertelement <4 x float> %890, float %44, i32 1
- %892 = insertelement <4 x float> %891, float %45, i32 2
- %893 = insertelement <4 x float> %892, float 0.000000e+00, i32 3
- %894 = insertelement <4 x float> undef, float %43, i32 0
- %895 = insertelement <4 x float> %894, float %44, i32 1
- %896 = insertelement <4 x float> %895, float %45, i32 2
- %897 = insertelement <4 x float> %896, float 0.000000e+00, i32 3
- %898 = call float @llvm.AMDGPU.dp4(<4 x float> %893, <4 x float> %897)
- %899 = call float @llvm.AMDGPU.rsq.f32(float %898)
- %900 = fmul float %45, %899
- %901 = call float @fabs(float %900)
- %902 = fmul float %176, 0x3FECCCCCC0000000
- %903 = fadd float %902, %901
- %904 = fadd float %903, 0xBFEFAE1480000000
- %905 = fmul float %904, 0xC043FFFE20000000
- %906 = call float @llvm.AMDIL.clamp.(float %905, float 0.000000e+00, float 1.000000e+00)
- %907 = fmul float 2.000000e+00, %906
- %908 = fsub float -0.000000e+00, %907
- %909 = fadd float 3.000000e+00, %908
- %910 = fmul float %906, %909
- %911 = fmul float %906, %910
- %912 = call float @llvm.AMDGPU.lrp(float %911, float %temp84.5, float %887)
- %913 = call float @llvm.AMDGPU.lrp(float %911, float %temp85.5, float %888)
- %914 = call float @llvm.AMDGPU.lrp(float %911, float %temp86.5, float %889)
- %915 = call float @llvm.AMDGPU.lrp(float %911, float %temp87.5, float 0.000000e+00)
- %916 = fmul float %202, 5.000000e-01
- %917 = fcmp uge float 0x3FE4CCCCC0000000, %916
- %918 = select i1 %917, float 0x3FE4CCCCC0000000, float %916
- %919 = fcmp uge float %918, 0x3FE3333340000000
- %920 = select i1 %919, float 0x3FE3333340000000, float %918
- %921 = call float @llvm.AMDGPU.lrp(float %920, float %912, float %temp84.5)
- %922 = call float @llvm.AMDGPU.lrp(float %920, float %913, float %temp85.5)
- %923 = call float @llvm.AMDGPU.lrp(float %920, float %914, float %temp86.5)
- %924 = call float @llvm.AMDGPU.lrp(float %920, float %915, float %temp87.5)
- %925 = insertelement <4 x float> undef, float %329, i32 0
- %926 = insertelement <4 x float> %925, float %330, i32 1
- %927 = insertelement <4 x float> %926, float %331, i32 2
- %928 = insertelement <4 x float> %927, float 0.000000e+00, i32 3
- %929 = insertelement <4 x float> undef, float %63, i32 0
- %930 = insertelement <4 x float> %929, float %65, i32 1
- %931 = insertelement <4 x float> %930, float %67, i32 2
- %932 = insertelement <4 x float> %931, float 0.000000e+00, i32 3
- %933 = call float @llvm.AMDGPU.dp4(<4 x float> %928, <4 x float> %932)
- %934 = fcmp uge float 0x3FE99999A0000000, %933
- %935 = select i1 %934, float 0x3FE99999A0000000, float %933
- %936 = fmul float %8, %935
- %937 = fmul float %13, %935
- %938 = fmul float %18, %935
- %939 = insertelement <4 x float> undef, float %34, i32 0
- %940 = insertelement <4 x float> %939, float %35, i32 1
- %941 = insertelement <4 x float> %940, float %36, i32 2
- %942 = insertelement <4 x float> %941, float 0.000000e+00, i32 3
- %943 = insertelement <4 x float> undef, float %63, i32 0
- %944 = insertelement <4 x float> %943, float %65, i32 1
- %945 = insertelement <4 x float> %944, float %67, i32 2
- %946 = insertelement <4 x float> %945, float 0.000000e+00, i32 3
- %947 = call float @llvm.AMDGPU.dp4(<4 x float> %942, <4 x float> %946)
- %948 = fcmp uge float 0x3FECCCCCC0000000, %947
- %949 = select i1 %948, float 0x3FECCCCCC0000000, float %947
- %950 = fmul float %936, %949
- %951 = fmul float %937, %949
- %952 = fmul float %938, %949
- br label %ENDIF178
-
-ENDIF178: ; preds = %ENDIF175, %IF179
- %temp84.6 = phi float [ %921, %IF179 ], [ %temp84.5, %ENDIF175 ]
- %temp85.6 = phi float [ %922, %IF179 ], [ %temp85.5, %ENDIF175 ]
- %temp86.6 = phi float [ %923, %IF179 ], [ %temp86.5, %ENDIF175 ]
- %temp87.6 = phi float [ %924, %IF179 ], [ %temp87.5, %ENDIF175 ]
- %temp92.12 = phi float [ %950, %IF179 ], [ %temp92.11, %ENDIF175 ]
- %temp93.6 = phi float [ %951, %IF179 ], [ %temp93.5, %ENDIF175 ]
- %temp94.6 = phi float [ %952, %IF179 ], [ %temp94.5, %ENDIF175 ]
- %953 = fmul float %55, %temp92.12
- %954 = fmul float %57, %temp93.6
- %955 = fmul float %59, %temp94.6
- %956 = fmul float %61, 0.000000e+00
- %957 = fmul float %temp84.6, %953
- %958 = fmul float %temp85.6, %954
- %959 = fmul float %temp86.6, %955
- %960 = fmul float %temp87.6, %956
- %961 = fmul float %2, -2.000000e+00
- %962 = fadd float %961, 1.000000e+00
- %963 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23)
- %964 = extractelement <4 x float> %963, i32 2
- %965 = fsub float -0.000000e+00, %964
- %966 = fadd float %962, %965
- %967 = fdiv float 1.000000e+00, %966
- %968 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24)
- %969 = extractelement <4 x float> %968, i32 2
- %970 = fmul float %969, %967
- %971 = fsub float -0.000000e+00, %53
- %972 = fmul float %971, %53
- %973 = fmul float %972, %970
- %974 = fmul float %973, %970
- %975 = fmul float %974, 0x3FF7154760000000
- %976 = call float @llvm.AMDIL.exp.(float %975)
- %977 = fcmp oeq float %53, 1.000000e+00
- %978 = sext i1 %977 to i32
- %979 = bitcast i32 %978 to float
- %980 = bitcast float %979 to i32
- %981 = icmp ne i32 %980, 0
- %.184 = select i1 %981, float 1.000000e+00, float %976
- %982 = call float @llvm.AMDGPU.lrp(float %.184, float %957, float %47)
- %983 = call float @llvm.AMDGPU.lrp(float %.184, float %958, float %49)
- %984 = call float @llvm.AMDGPU.lrp(float %.184, float %959, float %51)
- %985 = insertelement <4 x float> undef, float %982, i32 0
- %986 = insertelement <4 x float> %985, float %983, i32 1
- %987 = insertelement <4 x float> %986, float %984, i32 2
- %988 = insertelement <4 x float> %987, float %960, i32 3
- call void @llvm.R600.store.swizzle(<4 x float> %988, i32 0, i32 0)
- ret void
-}
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.rsq.f32(float) #1
-
-; Function Attrs: readnone
-declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
-
-; Function Attrs: readonly
-declare float @fabs(float) #2
-
-; Function Attrs: readnone
-declare float @llvm.AMDIL.exp.(float) #1
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.lrp(float, float, float) #1
-
-; Function Attrs: readnone
-declare float @llvm.AMDIL.clamp.(float, float, float) #1
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
-attributes #1 = { readnone }
-attributes #2 = { readonly }
Removed: llvm/trunk/test/CodeGen/R600/bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/bitcast.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/R600/bitcast.ll (removed)
@@ -1,79 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; This test just checks that the compiler doesn't crash.
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-; FUNC-LABEL: {{^}}v32i8_to_v8i32:
-; SI: s_endpgm
-define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 {
-entry:
- %1 = load <32 x i8>, <32 x i8> addrspace(2)* %0
- %2 = bitcast <32 x i8> %1 to <8 x i32>
- %3 = extractelement <8 x i32> %2, i32 1
- %4 = icmp ne i32 %3, 0
- %5 = select i1 %4, float 0.0, float 1.0
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5)
- ret void
-}
-
-; FUNC-LABEL: {{^}}i8ptr_v16i8ptr:
-; SI: s_endpgm
-define void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) {
-entry:
- %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)*
- %1 = load <16 x i8>, <16 x i8> addrspace(1)* %0
- store <16 x i8> %1, <16 x i8> addrspace(1)* %out
- ret void
-}
-
-define void @f32_to_v2i16(<2 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %load = load float, float addrspace(1)* %in, align 4
- %bc = bitcast float %load to <2 x i16>
- store <2 x i16> %bc, <2 x i16> addrspace(1)* %out, align 4
- ret void
-}
-
-define void @v2i16_to_f32(float addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind {
- %load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4
- %bc = bitcast <2 x i16> %load to float
- store float %bc, float addrspace(1)* %out, align 4
- ret void
-}
-
-define void @v4i8_to_i32(i32 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- %bc = bitcast <4 x i8> %load to i32
- store i32 %bc, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-define void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %bc = bitcast i32 %load to <4 x i8>
- store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64:
-; SI: s_endpgm
-define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
- %add = add <2 x i32> %val, <i32 4, i32 9>
- %bc = bitcast <2 x i32> %add to double
- store double %bc, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32:
-; SI: s_endpgm
-define void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace(1)* %in) {
- %val = load double, double addrspace(1)* %in, align 8
- %add = fadd double %val, 4.0
- %bc = bitcast double %add to <2 x i32>
- store <2 x i32> %bc, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-attributes #0 = { "ShaderType"="0" }
Removed: llvm/trunk/test/CodeGen/R600/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/bswap.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/R600/bswap.ll (removed)
@@ -1,115 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.bswap.i32(i32) nounwind readnone
-declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
-declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
-declare i64 @llvm.bswap.i64(i64) nounwind readnone
-declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
-declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
-
-; FUNC-LABEL: @test_bswap_i32
-; SI: buffer_load_dword [[VAL:v[0-9]+]]
-; SI-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
-; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
-; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
-; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
- store i32 %bswap, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_bswap_v2i32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI: s_endpgm
-define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
- %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
- store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_bswap_v4i32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI: s_endpgm
-define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
- %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
- %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
- store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_bswap_v8i32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_alignbit_b32
-; SI-DAG: v_bfi_b32
-; SI: s_endpgm
-define void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
- %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
- %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
- store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
- ret void
-}
-
-define void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
- %val = load i64, i64 addrspace(1)* %in, align 8
- %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
- store i64 %bswap, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-define void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
- %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
- %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
- store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
- ret void
-}
-
-define void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
- %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
- %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
- store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/build_vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/build_vector.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/build_vector.ll (original)
+++ llvm/trunk/test/CodeGen/R600/build_vector.ll (removed)
@@ -1,35 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI
-
-; R600: {{^}}build_vector2:
-; R600: MOV
-; R600: MOV
-; R600-NOT: MOV
-; SI: {{^}}build_vector2:
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
-; SI: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}}
-define void @build_vector2 (<2 x i32> addrspace(1)* %out) {
-entry:
- store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; R600: {{^}}build_vector4:
-; R600: MOV
-; R600: MOV
-; R600: MOV
-; R600: MOV
-; R600-NOT: MOV
-; SI: {{^}}build_vector4:
-; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
-; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
-; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
-; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
-; SI: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}}
-define void @build_vector4 (<4 x i32> addrspace(1)* %out) {
-entry:
- store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/call.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/call.ll (original)
+++ llvm/trunk/test/CodeGen/R600/call.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: not llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s 2>&1 | FileCheck %s
-; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s 2>&1 | FileCheck %s
-; RUN: not llc -march=r600 -mcpu=cypress < %s 2>&1 | FileCheck %s
-
-; CHECK: error: unsupported call to function external_function in test_call_external
-
-
-declare i32 @external_function(i32) nounwind
-
-define void @test_call_external(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
- %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %a = load i32, i32 addrspace(1)* %in
- %b = load i32, i32 addrspace(1)* %b_ptr
- %c = call i32 @external_function(i32 %b) nounwind
- %result = add i32 %a, %c
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
-
-define i32 @defined_function(i32 %x) nounwind noinline {
- %y = add i32 %x, 8
- ret i32 %y
-}
-
-define void @test_call(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
- %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %a = load i32, i32 addrspace(1)* %in
- %b = load i32, i32 addrspace(1)* %b_ptr
- %c = call i32 @defined_function(i32 %b) nounwind
- %result = add i32 %a, %c
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/call_fs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/call_fs.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/call_fs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/call_fs.ll (removed)
@@ -1,17 +0,0 @@
-
-; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s
-; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s
-
-; EG: .long 257
-; EG: {{^}}call_fs:
-; EG: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84]
-; R600: .long 257
-; R600: {{^}}call_fs:
-; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
-
-
-define void @call_fs() #0 {
- ret void
-}
-
-attributes #0 = { "ShaderType"="1" } ; Vertex Shader
Removed: llvm/trunk/test/CodeGen/R600/cayman-loop-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cayman-loop-bug.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cayman-loop-bug.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cayman-loop-bug.ll (removed)
@@ -1,32 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
-
-; CHECK-LABEL: {{^}}main:
-; CHECK: LOOP_START_DX10
-; CHECK: ALU_PUSH_BEFORE
-; CHECK: LOOP_START_DX10
-; CHECK: PUSH
-; CHECK-NOT: ALU_PUSH_BEFORE
-; CHECK: END_LOOP
-; CHECK: END_LOOP
-define void @main (<4 x float> inreg %reg0) #0 {
-entry:
- br label %outer_loop
-outer_loop:
- %cnt = phi i32 [0, %entry], [%cnt_incr, %inner_loop]
- %cond = icmp eq i32 %cnt, 16
- br i1 %cond, label %outer_loop_body, label %exit
-outer_loop_body:
- %cnt_incr = add i32 %cnt, 1
- br label %inner_loop
-inner_loop:
- %cnt2 = phi i32 [0, %outer_loop_body], [%cnt2_incr, %inner_loop_body]
- %cond2 = icmp eq i32 %cnt2, 16
- br i1 %cond, label %inner_loop_body, label %outer_loop
-inner_loop_body:
- %cnt2_incr = add i32 %cnt2, 1
- br label %inner_loop
-exit:
- ret void
-}
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/cf-stack-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cf-stack-bug.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cf-stack-bug.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cf-stack-bug.ll (removed)
@@ -1,244 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG64 %s < %t
-
-; RUN: llc -march=r600 -mcpu=sumo -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG64 %s < %t
-
-; RUN: llc -march=r600 -mcpu=barts -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG64 %s < %t
-
-; RUN: llc -march=r600 -mcpu=turks -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG64 %s < %t
-
-; RUN: llc -march=r600 -mcpu=caicos -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG64 %s < %t
-
-; RUN: llc -march=r600 -mcpu=cedar -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=BUG32 %s < %t
-
-; RUN: llc -march=r600 -mcpu=juniper -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=NOBUG %s < %t
-
-; RUN: llc -march=r600 -mcpu=cypress -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=NOBUG %s < %t
-
-; RUN: llc -march=r600 -mcpu=cayman -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
-; RUN: FileCheck --check-prefix=NOBUG %s < %t
-
-; REQUIRES: asserts
-
-; We are currently allocating 2 extra sub-entries on Evergreen / NI for
-; non-WQM push instructions if we change this to 1, then we will need to
-; add one level of depth to each of these tests.
-
-; BUG64-NOT: Applying bug work-around
-; BUG32-NOT: Applying bug work-around
-; NOBUG-NOT: Applying bug work-around
-; FUNC-LABEL: {{^}}nested3:
-define void @nested3(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp sgt i32 %cond, 0
- br i1 %0, label %if.1, label %end
-
-if.1:
- %1 = icmp sgt i32 %cond, 10
- br i1 %1, label %if.2, label %if.store.1
-
-if.store.1:
- store i32 1, i32 addrspace(1)* %out
- br label %end
-
-if.2:
- %2 = icmp sgt i32 %cond, 20
- br i1 %2, label %if.3, label %if.2.store
-
-if.2.store:
- store i32 2, i32 addrspace(1)* %out
- br label %end
-
-if.3:
- store i32 3, i32 addrspace(1)* %out
- br label %end
-
-end:
- ret void
-}
-
-; BUG64: Applying bug work-around
-; BUG32-NOT: Applying bug work-around
-; NOBUG-NOT: Applying bug work-around
-; FUNC-LABEL: {{^}}nested4:
-define void @nested4(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp sgt i32 %cond, 0
- br i1 %0, label %if.1, label %end
-
-if.1:
- %1 = icmp sgt i32 %cond, 10
- br i1 %1, label %if.2, label %if.1.store
-
-if.1.store:
- store i32 1, i32 addrspace(1)* %out
- br label %end
-
-if.2:
- %2 = icmp sgt i32 %cond, 20
- br i1 %2, label %if.3, label %if.2.store
-
-if.2.store:
- store i32 2, i32 addrspace(1)* %out
- br label %end
-
-if.3:
- %3 = icmp sgt i32 %cond, 30
- br i1 %3, label %if.4, label %if.3.store
-
-if.3.store:
- store i32 3, i32 addrspace(1)* %out
- br label %end
-
-if.4:
- store i32 4, i32 addrspace(1)* %out
- br label %end
-
-end:
- ret void
-}
-
-; BUG64: Applying bug work-around
-; BUG32-NOT: Applying bug work-around
-; NOBUG-NOT: Applying bug work-around
-; FUNC-LABEL: {{^}}nested7:
-define void @nested7(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp sgt i32 %cond, 0
- br i1 %0, label %if.1, label %end
-
-if.1:
- %1 = icmp sgt i32 %cond, 10
- br i1 %1, label %if.2, label %if.1.store
-
-if.1.store:
- store i32 1, i32 addrspace(1)* %out
- br label %end
-
-if.2:
- %2 = icmp sgt i32 %cond, 20
- br i1 %2, label %if.3, label %if.2.store
-
-if.2.store:
- store i32 2, i32 addrspace(1)* %out
- br label %end
-
-if.3:
- %3 = icmp sgt i32 %cond, 30
- br i1 %3, label %if.4, label %if.3.store
-
-if.3.store:
- store i32 3, i32 addrspace(1)* %out
- br label %end
-
-if.4:
- %4 = icmp sgt i32 %cond, 40
- br i1 %4, label %if.5, label %if.4.store
-
-if.4.store:
- store i32 4, i32 addrspace(1)* %out
- br label %end
-
-if.5:
- %5 = icmp sgt i32 %cond, 50
- br i1 %5, label %if.6, label %if.5.store
-
-if.5.store:
- store i32 5, i32 addrspace(1)* %out
- br label %end
-
-if.6:
- %6 = icmp sgt i32 %cond, 60
- br i1 %6, label %if.7, label %if.6.store
-
-if.6.store:
- store i32 6, i32 addrspace(1)* %out
- br label %end
-
-if.7:
- store i32 7, i32 addrspace(1)* %out
- br label %end
-
-end:
- ret void
-}
-
-; BUG64: Applying bug work-around
-; BUG32: Applying bug work-around
-; NOBUG-NOT: Applying bug work-around
-; FUNC-LABEL: {{^}}nested8:
-define void @nested8(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp sgt i32 %cond, 0
- br i1 %0, label %if.1, label %end
-
-if.1:
- %1 = icmp sgt i32 %cond, 10
- br i1 %1, label %if.2, label %if.1.store
-
-if.1.store:
- store i32 1, i32 addrspace(1)* %out
- br label %end
-
-if.2:
- %2 = icmp sgt i32 %cond, 20
- br i1 %2, label %if.3, label %if.2.store
-
-if.2.store:
- store i32 2, i32 addrspace(1)* %out
- br label %end
-
-if.3:
- %3 = icmp sgt i32 %cond, 30
- br i1 %3, label %if.4, label %if.3.store
-
-if.3.store:
- store i32 3, i32 addrspace(1)* %out
- br label %end
-
-if.4:
- %4 = icmp sgt i32 %cond, 40
- br i1 %4, label %if.5, label %if.4.store
-
-if.4.store:
- store i32 4, i32 addrspace(1)* %out
- br label %end
-
-if.5:
- %5 = icmp sgt i32 %cond, 50
- br i1 %5, label %if.6, label %if.5.store
-
-if.5.store:
- store i32 5, i32 addrspace(1)* %out
- br label %end
-
-if.6:
- %6 = icmp sgt i32 %cond, 60
- br i1 %6, label %if.7, label %if.6.store
-
-if.6.store:
- store i32 6, i32 addrspace(1)* %out
- br label %end
-
-if.7:
- %7 = icmp sgt i32 %cond, 70
- br i1 %7, label %if.8, label %if.7.store
-
-if.7.store:
- store i32 7, i32 addrspace(1)* %out
- br label %end
-
-if.8:
- store i32 8, i32 addrspace(1)* %out
- br label %end
-
-end:
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/cf_end.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cf_end.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cf_end.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cf_end.ll (removed)
@@ -1,9 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG %s
-; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG %s
-; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM %s
-
-; EG: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80]
-; CM: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88]
-define void @eop() {
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll (removed)
@@ -1,242 +0,0 @@
-; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=OPT %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s
-
-declare i32 @llvm.r600.read.tidig.x() #0
-
-; OPT-LABEL: @test_sink_global_small_offset_i32(
-; OPT-NOT: getelementptr i32, i32 addrspace(1)* %in
-; OPT: br i1
-; OPT: ptrtoint
-
-; GCN-LABEL: {{^}}test_sink_global_small_offset_i32:
-; GCN: {{^}}BB0_2:
-define void @test_sink_global_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond) {
-entry:
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
- %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 7
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i32, i32 addrspace(1)* %in.gep
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-; OPT-LABEL: @test_sink_global_small_max_i32_ds_offset(
-; OPT: %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535
-; OPT: br i1
-
-; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
-; GCN: {{^}}BB1_2:
-; GCN: s_or_b64 exec
-define void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
-entry:
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
- %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i8, i8 addrspace(1)* %in.gep
- %tmp2 = sext i8 %tmp1 to i32
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}
-; GCN: {{^}}BB2_2:
-; GCN: s_or_b64 exec
-define void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
-entry:
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024
- %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i8, i8 addrspace(1)* %in.gep
- %tmp2 = sext i8 %tmp1 to i32
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
-; GCN: {{^}}BB3_2:
-; GCN: s_or_b64 exec
-define void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
-entry:
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
- %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i8, i8 addrspace(1)* %in.gep
- %tmp2 = sext i8 %tmp1 to i32
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-; OPT-LABEL: @test_no_sink_flat_small_offset_i32(
-; OPT: getelementptr i32, i32 addrspace(4)* %in
-; OPT: br i1
-; OPT-NOT: ptrtoint
-
-; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:
-; GCN: flat_load_dword
-; GCN: {{^}}BB4_2:
-
-define void @test_no_sink_flat_small_offset_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) {
-entry:
- %out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999
- %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i32, i32 addrspace(4)* %in.gep
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(4)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-; OPT-LABEL: @test_sink_scratch_small_offset_i32(
-; OPT-NOT: getelementptr [512 x i32]
-; OPT: br i1
-; OPT: ptrtoint
-
-; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
-; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
-; GCN: {{^}}BB5_2:
-define void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {
-entry:
- %alloca = alloca [512 x i32], align 4
- %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
- %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
- %add.arg = add i32 %arg, 8
- %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1023
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- store volatile i32 123, i32* %alloca.gep
- %tmp1 = load volatile i32, i32* %alloca.gep
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep.0
- %load = load volatile i32, i32* %alloca.gep
- store i32 %load, i32 addrspace(1)* %out.gep.1
- br label %done
-
-done:
- ret void
-}
-
-; OPT-LABEL: @test_no_sink_scratch_large_offset_i32(
-; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024
-; OPT: br i1
-; OPT-NOT: ptrtoint
-
-; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
-; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
-; GCN: {{^}}BB6_2:
-define void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {
-entry:
- %alloca = alloca [512 x i32], align 4
- %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
- %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
- %add.arg = add i32 %arg, 8
- %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- store volatile i32 123, i32* %alloca.gep
- %tmp1 = load volatile i32, i32* %alloca.gep
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep.0
- %load = load volatile i32, i32* %alloca.gep
- store i32 %load, i32 addrspace(1)* %out.gep.1
- br label %done
-
-done:
- ret void
-}
-
-; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32:
-; GCN: s_and_saveexec_b64
-; GCN: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; GCN: {{^}}BB7_2:
-define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset, i32 %cond) {
-entry:
- %offset.ext = zext i32 %offset to i64
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
- %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %endif, label %if
-
-if:
- %tmp1 = load i32, i32 addrspace(1)* %in.gep
- br label %endif
-
-endif:
- %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
- store i32 %x, i32 addrspace(1)* %out.gep
- br label %done
-
-done:
- ret void
-}
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/coalescer_remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/coalescer_remat.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/coalescer_remat.ll (original)
+++ llvm/trunk/test/CodeGen/R600/coalescer_remat.ll (removed)
@@ -1,57 +0,0 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s
-
-declare float @llvm.fma.f32(float, float, float)
-
-; This checks that rematerialization support of the coalescer does not
-; unnecessarily widen the register class. Without those fixes > 20 VGprs
-; are used here
-; Also check that some rematerialization of the 0 constant happened.
-; CHECK-LABEL: foobar
-; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
-; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
-; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
-; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 0
-; It's probably OK if this is slightly higher:
-; CHECK: ; NumVgprs: 9
-define void @foobar(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %flag) {
-entry:
- %cmpflag = icmp eq i32 %flag, 1
- br i1 %cmpflag, label %loop, label %exit
-
-loop:
- %c = phi i32 [0, %entry], [%cnext, %loop]
- %v0 = phi float [0.0, %entry], [%fma.0, %loop]
- %v1 = phi float [0.0, %entry], [%fma.1, %loop]
- %v2 = phi float [0.0, %entry], [%fma.2, %loop]
- %v3 = phi float [0.0, %entry], [%fma.3, %loop]
-
- ; Try to get the 0 constant to get coalesced into a wide register
- %blup = insertelement <4 x float> undef, float %v0, i32 0
- store <4 x float> %blup, <4 x float> addrspace(1)* %out
-
- %load = load <4 x float>, <4 x float> addrspace(1)* %in
- %load.0 = extractelement <4 x float> %load, i32 0
- %load.1 = extractelement <4 x float> %load, i32 1
- %load.2 = extractelement <4 x float> %load, i32 2
- %load.3 = extractelement <4 x float> %load, i32 3
- %fma.0 = call float @llvm.fma.f32(float %v0, float %load.0, float %v0)
- %fma.1 = call float @llvm.fma.f32(float %v1, float %load.1, float %v1)
- %fma.2 = call float @llvm.fma.f32(float %v2, float %load.2, float %v2)
- %fma.3 = call float @llvm.fma.f32(float %v3, float %load.3, float %v3)
-
- %cnext = add nsw i32 %c, 1
- %cmp = icmp eq i32 %cnext, 42
- br i1 %cmp, label %exit, label %loop
-
-exit:
- %ev0 = phi float [0.0, %entry], [%fma.0, %loop]
- %ev1 = phi float [0.0, %entry], [%fma.1, %loop]
- %ev2 = phi float [0.0, %entry], [%fma.2, %loop]
- %ev3 = phi float [0.0, %entry], [%fma.3, %loop]
- %dst.0 = insertelement <4 x float> undef, float %ev0, i32 0
- %dst.1 = insertelement <4 x float> %dst.0, float %ev1, i32 1
- %dst.2 = insertelement <4 x float> %dst.1, float %ev2, i32 2
- %dst.3 = insertelement <4 x float> %dst.2, float %ev3, i32 3
- store <4 x float> %dst.3, <4 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll (original)
+++ llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: opt -mtriple=amdgcn-- -codegenprepare -S < %s | FileCheck -check-prefix=OPT %s
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-LLC %s
-
-; OPT-LABEL: @test(
-; OPT: mul nsw i32
-; OPT-NEXT: sext
-
-; SI-LLC-LABEL: {{^}}test:
-; SI-LLC: s_mul_i32
-; SI-LLC-NOT: mul
-define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) {
-entry:
- %0 = mul nsw i32 %a, 3
- %1 = sext i32 %0 to i64
- %2 = getelementptr i8, i8 addrspace(1)* %in, i64 %1
- store i8 %b, i8 addrspace(1)* %2
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/combine_vloads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/combine_vloads.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/combine_vloads.ll (original)
+++ llvm/trunk/test/CodeGen/R600/combine_vloads.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
-
-;
-; kernel void combine_vloads(global char8* src, global char8* result) {
-; for (int i = 0; i < 1024; ++i)
-; result[i] = src[0] + src[1] + src[2] + src[3];
-; }
-;
-
-
-; 128-bit loads instead of many 8-bit
-; EG-LABEL: {{^}}combine_vloads:
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-define void @combine_vloads(<8 x i8> addrspace(1)* nocapture %src, <8 x i8> addrspace(1)* nocapture %result) nounwind {
-entry:
- br label %for.body
-
-for.exit: ; preds = %for.body
- ret void
-
-for.body: ; preds = %for.body, %entry
- %i.01 = phi i32 [ 0, %entry ], [ %tmp19, %for.body ]
- %arrayidx_v4 = bitcast <8 x i8> addrspace(1)* %src to <32 x i8> addrspace(1)*
- %0 = bitcast <32 x i8> addrspace(1)* %arrayidx_v4 to <8 x i32> addrspace(1)*
- %vecload2 = load <8 x i32>, <8 x i32> addrspace(1)* %0, align 32
- %1 = bitcast <8 x i32> %vecload2 to <32 x i8>
- %tmp5 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %tmp8 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp9 = add nsw <8 x i8> %tmp5, %tmp8
- %tmp12 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
- %tmp13 = add nsw <8 x i8> %tmp9, %tmp12
- %tmp16 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- %tmp17 = add nsw <8 x i8> %tmp13, %tmp16
- %scevgep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %result, i32 %i.01
- %2 = bitcast <8 x i8> %tmp17 to <2 x i32>
- %3 = bitcast <8 x i8> addrspace(1)* %scevgep to <2 x i32> addrspace(1)*
- store <2 x i32> %2, <2 x i32> addrspace(1)* %3, align 8
- %tmp19 = add nsw i32 %i.01, 1
- %exitcond = icmp eq i32 %tmp19, 1024
- br i1 %exitcond, label %for.exit, label %for.body
-}
Removed: llvm/trunk/test/CodeGen/R600/commute-compares.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/commute-compares.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/commute-compares.ll (original)
+++ llvm/trunk/test/CodeGen/R600/commute-compares.ll (removed)
@@ -1,697 +0,0 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-
-declare i32 @llvm.r600.read.tidig.x() #0
-
-; --------------------------------------------------------------------------------
-; i32 compares
-; --------------------------------------------------------------------------------
-
-; GCN-LABEL: {{^}}commute_eq_64_i32:
-; GCN: v_cmp_eq_i32_e32 vcc, 64, v{{[0-9]+}}
-define void @commute_eq_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp eq i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ne_64_i32:
-; GCN: v_cmp_ne_i32_e32 vcc, 64, v{{[0-9]+}}
-define void @commute_ne_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ne i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; FIXME: Why isn't this being folded as a constant?
-; GCN-LABEL: {{^}}commute_ne_litk_i32:
-; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3039
-; GCN: v_cmp_ne_i32_e32 vcc, [[K]], v{{[0-9]+}}
-define void @commute_ne_litk_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ne i32 %val, 12345
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ugt_64_i32:
-; GCN: v_cmp_lt_u32_e32 vcc, 64, v{{[0-9]+}}
-define void @commute_ugt_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ugt i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uge_64_i32:
-; GCN: v_cmp_lt_u32_e32 vcc, 63, v{{[0-9]+}}
-define void @commute_uge_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp uge i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ult_64_i32:
-; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
-define void @commute_ult_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ult i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ule_63_i32:
-; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}}
-define void @commute_ule_63_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ule i32 %val, 63
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm
-
-; GCN-LABEL: {{^}}commute_ule_64_i32:
-; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x41{{$}}
-; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}}
-define void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp ule i32 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sgt_neg1_i32:
-; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}}
-define void @commute_sgt_neg1_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp sgt i32 %val, -1
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sge_neg2_i32:
-; GCN: v_cmp_lt_i32_e32 vcc, -3, v{{[0-9]+}}
-define void @commute_sge_neg2_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp sge i32 %val, -2
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_slt_neg16_i32:
-; GCN: v_cmp_gt_i32_e32 vcc, -16, v{{[0-9]+}}
-define void @commute_slt_neg16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp slt i32 %val, -16
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sle_5_i32:
-; GCN: v_cmp_gt_i32_e32 vcc, 6, v{{[0-9]+}}
-define void @commute_sle_5_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i32, i32 addrspace(1)* %gep.in
- %cmp = icmp sle i32 %val, 5
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; --------------------------------------------------------------------------------
-; i64 compares
-; --------------------------------------------------------------------------------
-
-; GCN-LABEL: {{^}}commute_eq_64_i64:
-; GCN: v_cmp_eq_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_eq_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp eq i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ne_64_i64:
-; GCN: v_cmp_ne_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ne_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp ne i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ugt_64_i64:
-; GCN: v_cmp_lt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ugt_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp ugt i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uge_64_i64:
-; GCN: v_cmp_lt_u64_e32 vcc, 63, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_uge_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp uge i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ult_64_i64:
-; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ult_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp ult i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ule_63_i64:
-; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ule_63_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp ule i64 %val, 63
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm
-
-; GCN-LABEL: {{^}}commute_ule_64_i64:
-; GCN-DAG: s_movk_i32 s[[KLO:[0-9]+]], 0x41{{$}}
-; GCN: v_cmp_gt_u64_e32 vcc, s{{\[}}[[KLO]]:{{[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp ule i64 %val, 64
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sgt_neg1_i64:
-; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_sgt_neg1_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp sgt i64 %val, -1
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sge_neg2_i64:
-; GCN: v_cmp_lt_i64_e32 vcc, -3, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_sge_neg2_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp sge i64 %val, -2
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_slt_neg16_i64:
-; GCN: v_cmp_gt_i64_e32 vcc, -16, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_slt_neg16_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp slt i64 %val, -16
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_sle_5_i64:
-; GCN: v_cmp_gt_i64_e32 vcc, 6, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_sle_5_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load i64, i64 addrspace(1)* %gep.in
- %cmp = icmp sle i64 %val, 5
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; --------------------------------------------------------------------------------
-; f32 compares
-; --------------------------------------------------------------------------------
-
-
-; GCN-LABEL: {{^}}commute_oeq_2.0_f32:
-; GCN: v_cmp_eq_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_oeq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp oeq float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-
-; GCN-LABEL: {{^}}commute_ogt_2.0_f32:
-; GCN: v_cmp_lt_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ogt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ogt float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_oge_2.0_f32:
-; GCN: v_cmp_le_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_oge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp oge float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_olt_2.0_f32:
-; GCN: v_cmp_gt_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_olt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp olt float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ole_2.0_f32:
-; GCN: v_cmp_ge_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ole_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ole float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_one_2.0_f32:
-; GCN: v_cmp_lg_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_one_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp one float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ord_2.0_f32:
-; GCN: v_cmp_o_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]]
-define void @commute_ord_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ord float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ueq_2.0_f32:
-; GCN: v_cmp_nlg_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ueq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ueq float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ugt_2.0_f32:
-; GCN: v_cmp_nge_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ugt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ugt float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uge_2.0_f32:
-; GCN: v_cmp_ngt_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_uge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp uge float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ult_2.0_f32:
-; GCN: v_cmp_nle_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ult_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ult float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ule_2.0_f32:
-; GCN: v_cmp_nlt_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_ule_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp ule float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_une_2.0_f32:
-; GCN: v_cmp_neq_f32_e32 vcc, 2.0, v{{[0-9]+}}
-define void @commute_une_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp une float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uno_2.0_f32:
-; GCN: v_cmp_u_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]]
-define void @commute_uno_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load float, float addrspace(1)* %gep.in
- %cmp = fcmp uno float %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; --------------------------------------------------------------------------------
-; f64 compares
-; --------------------------------------------------------------------------------
-
-
-; GCN-LABEL: {{^}}commute_oeq_2.0_f64:
-; GCN: v_cmp_eq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_oeq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp oeq double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-
-; GCN-LABEL: {{^}}commute_ogt_2.0_f64:
-; GCN: v_cmp_lt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ogt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ogt double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_oge_2.0_f64:
-; GCN: v_cmp_le_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_oge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp oge double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_olt_2.0_f64:
-; GCN: v_cmp_gt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_olt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp olt double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ole_2.0_f64:
-; GCN: v_cmp_ge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ole_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ole double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_one_2.0_f64:
-; GCN: v_cmp_lg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_one_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp one double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ord_2.0_f64:
-; GCN: v_cmp_o_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]]
-define void @commute_ord_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ord double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ueq_2.0_f64:
-; GCN: v_cmp_nlg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ueq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ueq double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ugt_2.0_f64:
-; GCN: v_cmp_nge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ugt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ugt double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uge_2.0_f64:
-; GCN: v_cmp_ngt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_uge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp uge double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ult_2.0_f64:
-; GCN: v_cmp_nle_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ult_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ult double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_ule_2.0_f64:
-; GCN: v_cmp_nlt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_ule_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp ule double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_une_2.0_f64:
-; GCN: v_cmp_neq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}}
-define void @commute_une_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp une double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-; GCN-LABEL: {{^}}commute_uno_2.0_f64:
-; GCN: v_cmp_u_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]]
-define void @commute_uno_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 {
- %tid = call i32 @llvm.r600.read.tidig.x() #0
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %val = load double, double addrspace(1)* %gep.in
- %cmp = fcmp uno double %val, 2.0
- %ext = sext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %gep.out
- ret void
-}
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/commute_modifiers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/commute_modifiers.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/commute_modifiers.ll (original)
+++ llvm/trunk/test/CodeGen/R600/commute_modifiers.ll (removed)
@@ -1,181 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() #1
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.fma.f32(float, float, float) nounwind readnone
-
-; FUNC-LABEL: @commute_add_imm_fabs_f32
-; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %x = load float, float addrspace(1)* %gep.0
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %z = fadd float 2.0, %x.fabs
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_mul_imm_fneg_fabs_f32
-; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_mul_f32_e64 [[REG:v[0-9]+]], -4.0, |[[X]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %x = load float, float addrspace(1)* %gep.0
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
- %z = fmul float 4.0, %x.fneg.fabs
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_mul_imm_fneg_f32
-; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_mul_f32_e32 [[REG:v[0-9]+]], -4.0, [[X]]
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %x = load float, float addrspace(1)* %gep.0
- %x.fneg = fsub float -0.000000e+00, %x
- %z = fmul float 4.0, %x.fneg
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FIXME: Should use SGPR for literal.
-; FUNC-LABEL: @commute_add_lit_fabs_f32
-; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_mov_b32_e32 [[K:v[0-9]+]], 0x44800000
-; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]]
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %x = load float, float addrspace(1)* %gep.0
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %z = fadd float 1024.0, %x.fabs
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_add_fabs_f32
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %x = load float, float addrspace(1)* %gep.0
- %y = load float, float addrspace(1)* %gep.1
- %y.fabs = call float @llvm.fabs.f32(float %y) #1
- %z = fadd float %x, %y.fabs
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_mul_fneg_f32
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -[[Y]]
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %x = load float, float addrspace(1)* %gep.0
- %y = load float, float addrspace(1)* %gep.1
- %y.fneg = fsub float -0.000000e+00, %y
- %z = fmul float %x, %y.fneg
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_mul_fabs_fneg_f32
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -|[[Y]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %x = load float, float addrspace(1)* %gep.0
- %y = load float, float addrspace(1)* %gep.1
- %y.fabs = call float @llvm.fabs.f32(float %y) #1
- %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
- %z = fmul float %x, %y.fabs.fneg
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; There's no reason to commute this.
-; FUNC-LABEL: @commute_mul_fabs_x_fabs_y_f32
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, |[[Y]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %x = load float, float addrspace(1)* %gep.0
- %y = load float, float addrspace(1)* %gep.1
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %y.fabs = call float @llvm.fabs.f32(float %y) #1
- %z = fmul float %x.fabs, %y.fabs
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @commute_mul_fabs_x_fneg_fabs_y_f32
-; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, -|[[Y]]|
-; SI-NEXT: buffer_store_dword [[REG]]
-define void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %x = load float, float addrspace(1)* %gep.0
- %y = load float, float addrspace(1)* %gep.1
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %y.fabs = call float @llvm.fabs.f32(float %y) #1
- %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
- %z = fmul float %x.fabs, %y.fabs.fneg
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; Make sure we commute the multiply part for the constant in src0 even
-; though we have negate modifier on src2.
-
-; SI-LABEL: {{^}}fma_a_2.0_neg_b_f32
-; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], |[[R2]]|
-; SI: buffer_store_dword [[RESULT]]
-define void @fma_a_2.0_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r2.fabs = call float @llvm.fabs.f32(float %r2)
-
- %r3 = tail call float @llvm.fma.f32(float %r1, float 2.0, float %r2.fabs)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/complex-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/complex-folding.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/complex-folding.ll (original)
+++ llvm/trunk/test/CodeGen/R600/complex-folding.ll (removed)
@@ -1,19 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}main:
-; CHECK-NOT: MOV
-define void @main(<4 x float> inreg %reg0) #0 {
-entry:
- %0 = extractelement <4 x float> %reg0, i32 0
- %1 = call float @fabs(float %0)
- %2 = fptoui float %1 to i32
- %3 = bitcast i32 %2 to float
- %4 = insertelement <4 x float> undef, float %3, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %4, i32 0, i32 0)
- ret void
-}
-
-declare float @fabs(float ) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/concat_vectors.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/concat_vectors.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/concat_vectors.ll (original)
+++ llvm/trunk/test/CodeGen/R600/concat_vectors.ll (removed)
@@ -1,296 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test_concat_v1i32:
-; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
-; instructions that access scratch memory. Bit 23, which is the add_tid_enable
-; bit, is only set for scratch access, so we can check for the absence of this
-; value if we want to ensure scratch memory is not being used.
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1i32(<2 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
- %concat = shufflevector <1 x i32> %a, <1 x i32> %b, <2 x i32> <i32 0, i32 1>
- store <2 x i32> %concat, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2i32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2i32(<4 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
- %concat = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x i32> %concat, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4i32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4i32(<8 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
- %concat = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x i32> %concat, <8 x i32> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8i32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8i32(<16 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) nounwind {
- %concat = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x i32> %concat, <16 x i32> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16i32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16i32(<32 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) nounwind {
- %concat = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x i32> %concat, <32 x i32> addrspace(1)* %out, align 128
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v1f32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1f32(<2 x float> addrspace(1)* %out, <1 x float> %a, <1 x float> %b) nounwind {
- %concat = shufflevector <1 x float> %a, <1 x float> %b, <2 x i32> <i32 0, i32 1>
- store <2 x float> %concat, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2f32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2f32(<4 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
- %concat = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x float> %concat, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4f32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4f32(<8 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
- %concat = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x float> %concat, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8f32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
- %concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x float> %concat, <16 x float> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16f32:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16f32(<32 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
- %concat = shufflevector <16 x float> %a, <16 x float> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x float> %concat, <32 x float> addrspace(1)* %out, align 128
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v1i64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1i64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind {
- %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>
- store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2i64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2i64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
- %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4i64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4i64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
- %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8i64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8i64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
- %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16i64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16i64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
- %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v1f64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1f64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind {
- %concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>
- store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2f64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2f64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
- %concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4f64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4f64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
- %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8f64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8f64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
- %concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16f64:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16f64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
- %concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v1i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1i1(<2 x i1> addrspace(1)* %out, <1 x i1> %a, <1 x i1> %b) nounwind {
- %concat = shufflevector <1 x i1> %a, <1 x i1> %b, <2 x i32> <i32 0, i32 1>
- store <2 x i1> %concat, <2 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2i1(<4 x i1> addrspace(1)* %out, <2 x i1> %a, <2 x i1> %b) nounwind {
- %concat = shufflevector <2 x i1> %a, <2 x i1> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x i1> %concat, <4 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4i1(<8 x i1> addrspace(1)* %out, <4 x i1> %a, <4 x i1> %b) nounwind {
- %concat = shufflevector <4 x i1> %a, <4 x i1> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x i1> %concat, <8 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8i1(<16 x i1> addrspace(1)* %out, <8 x i1> %a, <8 x i1> %b) nounwind {
- %concat = shufflevector <8 x i1> %a, <8 x i1> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x i1> %concat, <16 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16i1(<32 x i1> addrspace(1)* %out, <16 x i1> %a, <16 x i1> %b) nounwind {
- %concat = shufflevector <16 x i1> %a, <16 x i1> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x i1> %concat, <32 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v32i1:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v32i1(<64 x i1> addrspace(1)* %out, <32 x i1> %a, <32 x i1> %b) nounwind {
- %concat = shufflevector <32 x i1> %a, <32 x i1> %b, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
- store <64 x i1> %concat, <64 x i1> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v1i16:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v1i16(<2 x i16> addrspace(1)* %out, <1 x i16> %a, <1 x i16> %b) nounwind {
- %concat = shufflevector <1 x i16> %a, <1 x i16> %b, <2 x i32> <i32 0, i32 1>
- store <2 x i16> %concat, <2 x i16> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v2i16:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v2i16(<4 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) nounwind {
- %concat = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x i16> %concat, <4 x i16> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v4i16:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v4i16(<8 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b) nounwind {
- %concat = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <8 x i16> %concat, <8 x i16> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v8i16:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v8i16(<16 x i16> addrspace(1)* %out, <8 x i16> %a, <8 x i16> %b) nounwind {
- %concat = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- store <16 x i16> %concat, <16 x i16> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_concat_v16i16:
-; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
-; SI-NOT: movrel
-define void @test_concat_v16i16(<32 x i16> addrspace(1)* %out, <16 x i16> %a, <16 x i16> %b) nounwind {
- %concat = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
- store <32 x i16> %concat, <32 x i16> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: {{^}}concat_vector_crash:
-; SI: s_endpgm
-define void @concat_vector_crash(<8 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
-bb:
- %tmp = load <2 x float>, <2 x float> addrspace(1)* %in, align 4
- %tmp1 = shufflevector <2 x float> %tmp, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
- %tmp2 = shufflevector <8 x float> undef, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
- store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/copy-illegal-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/copy-illegal-type.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/copy-illegal-type.ll (original)
+++ llvm/trunk/test/CodeGen/R600/copy-illegal-type.ll (removed)
@@ -1,167 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test_copy_v4i8:
-; SI: buffer_load_dword [[REG:v[0-9]+]]
-; SI: buffer_store_dword [[REG]]
-; SI: s_endpgm
-define void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_x2:
-; SI: buffer_load_dword [[REG:v[0-9]+]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: s_endpgm
-define void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_x3:
-; SI: buffer_load_dword [[REG:v[0-9]+]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: s_endpgm
-define void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_x4:
-; SI: buffer_load_dword [[REG:v[0-9]+]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: buffer_store_dword [[REG]]
-; SI: s_endpgm
-define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out1, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out3, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_extra_use:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI_DAG: buffer_store_byte
-
-; After scalarizing v4i8 loads is fixed.
-; XSI: buffer_load_dword
-; XSI: V_BFE
-; XSI: V_ADD
-; XSI: V_ADD
-; XSI: V_ADD
-; XSI: buffer_store_dword
-; XSI: buffer_store_dword
-
-; SI: s_endpgm
-define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
- store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_x2_extra_use:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: v_add
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI_DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI-DAG: buffer_store_byte
-; SI_DAG: buffer_store_byte
-
-; XSI: buffer_load_dword
-; XSI: BFE
-; XSI: buffer_store_dword
-; XSI: V_ADD
-; XSI: buffer_store_dword
-; XSI-NEXT: buffer_store_dword
-
-; SI: s_endpgm
-define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- %add = add <4 x i8> %val, <i8 9, i8 9, i8 9, i8 9>
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out0, align 4
- store <4 x i8> %add, <4 x i8> addrspace(1)* %out1, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out2, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v3i8:
-; SI-NOT: bfe
-; SI-NOT: bfi
-; SI: s_endpgm
-define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
- %val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
- store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_load:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: s_endpgm
-define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_store:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: s_endpgm
-define void @test_copy_v4i8_volatile_store(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
- %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/copy-to-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/copy-to-reg.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/copy-to-reg.ll (original)
+++ llvm/trunk/test/CodeGen/R600/copy-to-reg.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s
-
-; Test that CopyToReg instructions don't have non-register operands prior
-; to being emitted.
-
-; Make sure this doesn't crash
-; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
-define void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
-entry:
- %alloca = alloca [16 x i32]
- br label %loop
-
-loop:
- %inc = phi i32 [0, %entry], [%inc.i, %loop]
- %ptr = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %inc
- store i32 %inc, i32* %ptr
- %inc.i = add i32 %inc, 1
- %cnd = icmp uge i32 %inc.i, 16
- br i1 %cnd, label %done, label %loop
-
-done:
- %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 0
- %tmp1 = load i32, i32* %tmp0
- store i32 %tmp1, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ctlz_zero_undef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ctlz_zero_undef.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ctlz_zero_undef.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ctlz_zero_undef.ll (removed)
@@ -1,71 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
-declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
-declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32:
-; SI: s_load_dword [[VAL:s[0-9]+]],
-; SI: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
- %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
- store i32 %ctlz, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
- %val = load i32, i32 addrspace(1)* %valptr, align 4
- %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
- store i32 %ctlz, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32:
-; SI: buffer_load_dwordx2
-; SI: v_ffbh_u32_e32
-; SI: v_ffbh_u32_e32
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
- %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
- store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32:
-; SI: buffer_load_dwordx4
-; SI: v_ffbh_u32_e32
-; SI: v_ffbh_u32_e32
-; SI: v_ffbh_u32_e32
-; SI: v_ffbh_u32_e32
-; SI: buffer_store_dwordx4
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-; EG: FFBH_UINT {{\*? *}}[[RESULT]]
-define void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
- %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
- %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
- store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ctpop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ctpop.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ctpop.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ctpop.ll (removed)
@@ -1,300 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC -check-prefix=VI %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.ctpop.i32(i32) nounwind readnone
-declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
-declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) nounwind readnone
-declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_ctpop_i32:
-; GCN: s_load_dword [[SVAL:s[0-9]+]],
-; GCN: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[SVAL]]
-; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; GCN: buffer_store_dword [[VRESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- store i32 %ctpop, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; XXX - Why 0 in register?
-; FUNC-LABEL: {{^}}v_ctpop_i32:
-; GCN: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- store i32 %ctpop, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32:
-; GCN: buffer_load_dword [[VAL1:v[0-9]+]],
-; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], [[VAL1]], 0
-; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
-; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-; EG: BCNT_INT
-define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1) nounwind {
- %val0 = load i32, i32 addrspace(1)* %in0, align 4
- %val1 = load i32, i32 addrspace(1)* %in1, align 4
- %ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
- %ctpop1 = call i32 @llvm.ctpop.i32(i32 %val1) nounwind readnone
- %add = add i32 %ctpop0, %ctpop1
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_add_sgpr_i32:
-; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
-; GCN-NEXT: s_waitcnt
-; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
-; GCN-NEXT: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1, i32 %sval) nounwind {
- %val0 = load i32, i32 addrspace(1)* %in0, align 4
- %ctpop0 = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
- %add = add i32 %ctpop0, %sval
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v2i32:
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-; EG: BCNT_INT
-define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) nounwind {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
- %ctpop = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %val) nounwind readnone
- store <2 x i32> %ctpop, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v4i32:
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %in) nounwind {
- %val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
- %ctpop = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val) nounwind readnone
- store <4 x i32> %ctpop, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v8i32:
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrspace(1)* noalias %in) nounwind {
- %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
- %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %val) nounwind readnone
- store <8 x i32> %ctpop, <8 x i32> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v16i32:
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: v_bcnt_u32_b32_e64
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-; EG: BCNT_INT
-define void @v_ctpop_v16i32(<16 x i32> addrspace(1)* noalias %out, <16 x i32> addrspace(1)* noalias %in) nounwind {
- %val = load <16 x i32>, <16 x i32> addrspace(1)* %in, align 32
- %ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
- store <16 x i32> %ctpop, <16 x i32> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant:
-; GCN: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32_add_inline_constant(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %add = add i32 %ctpop, 4
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_inline_constant_inv:
-; GCN: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %add = add i32 4, %ctpop
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_literal:
-; GCN: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f
-; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
-; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-define void @v_ctpop_i32_add_literal(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %add = add i32 %ctpop, 99999
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_var:
-; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN-DAG: s_load_dword [[VAR:s[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32_add_var(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %add = add i32 %ctpop, %const
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_var_inv:
-; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]],
-; GCN-DAG: s_load_dword [[VAR:s[0-9]+]],
-; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %const) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %add = add i32 %const, %ctpop
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i32_add_vvar_inv:
-; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}}
-; GCN-DAG: buffer_load_dword [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:16
-; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BCNT_INT
-define void @v_ctpop_i32_add_vvar_inv(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 addrspace(1)* noalias %constptr) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
- %gep = getelementptr i32, i32 addrspace(1)* %constptr, i32 4
- %const = load i32, i32 addrspace(1)* %gep, align 4
- %add = add i32 %const, %ctpop
- store i32 %add, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FIXME: We currently disallow SALU instructions in all branches,
-; but there are some cases when the should be allowed.
-
-; FUNC-LABEL: {{^}}ctpop_i32_in_br:
-; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xd
-; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x34
-; GCN: s_bcnt1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
-; GCN: v_mov_b32_e32 [[RESULT]], [[SRESULT]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-; EG: BCNT_INT
-define void @ctpop_i32_in_br(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %ctpop_arg, i32 %cond) {
-entry:
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %if, label %else
-
-if:
- %tmp2 = call i32 @llvm.ctpop.i32(i32 %ctpop_arg)
- br label %endif
-
-else:
- %tmp3 = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %tmp4 = load i32, i32 addrspace(1)* %tmp3
- br label %endif
-
-endif:
- %tmp5 = phi i32 [%tmp2, %if], [%tmp4, %else]
- store i32 %tmp5, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ctpop64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ctpop64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ctpop64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ctpop64.ll (removed)
@@ -1,124 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-
-declare i64 @llvm.ctpop.i64(i64) nounwind readnone
-declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
-declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
-declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
-declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_ctpop_i64:
-; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
-; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; GCN: buffer_store_dword [[VRESULT]],
-; GCN: s_endpgm
-define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
- %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
- %truncctpop = trunc i64 %ctpop to i32
- store i32 %truncctpop, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_i64:
-; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
-; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
-; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
- %val = load i64, i64 addrspace(1)* %in, align 8
- %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
- %truncctpop = trunc i64 %ctpop to i32
- store i32 %truncctpop, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_ctpop_v2i64:
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_endpgm
-define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind {
- %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
- %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
- store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_ctpop_v4i64:
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_endpgm
-define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind {
- %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
- %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
- store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v2i64:
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: s_endpgm
-define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind {
- %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
- %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
- %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
- store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_ctpop_v4i64:
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: s_endpgm
-define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
- %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
- %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
- %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
- store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; FIXME: We currently disallow SALU instructions in all branches,
-; but there are some cases when the should be allowed.
-
-; FUNC-LABEL: {{^}}ctpop_i64_in_br:
-; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd
-; VI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34
-; GCN: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
-; GCN: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
-; GCN: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]]
-; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
-; GCN: s_endpgm
-define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
-entry:
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %if, label %else
-
-if:
- %tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg)
- br label %endif
-
-else:
- %tmp3 = getelementptr i64, i64 addrspace(1)* %in, i32 1
- %tmp4 = load i64, i64 addrspace(1)* %tmp3
- br label %endif
-
-endif:
- %tmp5 = phi i64 [%tmp2, %if], [%tmp4, %else]
- store i64 %tmp5, i64 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/cttz_zero_undef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cttz_zero_undef.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cttz_zero_undef.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cttz_zero_undef.ll (removed)
@@ -1,71 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
-declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
-declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_cttz_zero_undef_i32:
-; SI: s_load_dword [[VAL:s[0-9]+]],
-; SI: s_ff1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
- %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
- store i32 %cttz, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_cttz_zero_undef_i32:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
- %val = load i32, i32 addrspace(1)* %valptr, align 4
- %cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
- store i32 %cttz, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_cttz_zero_undef_v2i32:
-; SI: buffer_load_dwordx2
-; SI: v_ffbl_b32_e32
-; SI: v_ffbl_b32_e32
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
- %cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
- store <2 x i32> %cttz, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_cttz_zero_undef_v4i32:
-; SI: buffer_load_dwordx4
-; SI: v_ffbl_b32_e32
-; SI: v_ffbl_b32_e32
-; SI: v_ffbl_b32_e32
-; SI: v_ffbl_b32_e32
-; SI: buffer_store_dwordx4
-; SI: s_endpgm
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-; EG: FFBL_INT {{\*? *}}[[RESULT]]
-define void @v_cttz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
- %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
- %cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
- store <4 x i32> %cttz, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/cvt_f32_ubyte.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cvt_f32_ubyte.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cvt_f32_ubyte.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cvt_f32_ubyte.ll (removed)
@@ -1,196 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}load_i8_to_f32:
-; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]],
-; SI-NOT: bfe
-; SI-NOT: lshr
-; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
-; SI: buffer_store_dword [[CONV]],
-define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
- %load = load i8, i8 addrspace(1)* %in, align 1
- %cvt = uitofp i8 %load to float
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}load_v2i8_to_v2f32:
-; SI: buffer_load_ushort [[LOADREG:v[0-9]+]],
-; SI-NOT: bfe
-; SI-NOT: lshr
-; SI-NOT: and
-; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
-; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
-define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2
- %cvt = uitofp <2 x i8> %load to <2 x float>
- store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}load_v3i8_to_v3f32:
-; SI-NOT: bfe
-; SI-NOT: v_cvt_f32_ubyte3_e32
-; SI-DAG: v_cvt_f32_ubyte2_e32
-; SI-DAG: v_cvt_f32_ubyte1_e32
-; SI-DAG: v_cvt_f32_ubyte0_e32
-; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
-define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4
- %cvt = uitofp <3 x i8> %load to <3 x float>
- store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}load_v4i8_to_v4f32:
-; SI: buffer_load_dword [[LOADREG:v[0-9]+]]
-; SI-NOT: bfe
-; SI-NOT: lshr
-; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
-; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
-; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
-; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
-define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- %cvt = uitofp <4 x i8> %load to <4 x float>
- store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; This should not be adding instructions to shift into the correct
-; position in the word for the component.
-
-; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned:
-; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]]
-; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
-; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
-; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
-; SI-NOT: v_lshlrev_b32
-; SI-NOT: v_or_b32
-
-; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG0]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG1]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG2]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]], [[LOADREG3]]
-
-; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
-define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
- %cvt = uitofp <4 x i8> %load to <4 x float>
- store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; XXX - This should really still be able to use the v_cvt_f32_ubyte0
-; for each component, but computeKnownBits doesn't handle vectors very
-; well.
-
-; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: v_cvt_f32_ubyte0_e32
-; SI: v_cvt_f32_ubyte0_e32
-; SI: v_cvt_f32_ubyte0_e32
-; SI: v_cvt_f32_ubyte0_e32
-
-; XXX - replace with this when v4i8 loads aren't scalarized anymore.
-; XSI: buffer_load_dword
-; XSI: v_cvt_f32_u32_e32
-; XSI: v_cvt_f32_u32_e32
-; XSI: v_cvt_f32_u32_e32
-; XSI: v_cvt_f32_u32_e32
-; SI: s_endpgm
-define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
- %cvt = uitofp <4 x i8> %load to <4 x float>
- store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
- %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
- store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
- ret void
-}
-
-; Make sure this doesn't crash.
-; SI-LABEL: {{^}}load_v7i8_to_v7f32:
-; SI: s_endpgm
-define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1
- %cvt = uitofp <7 x i8> %load to <7 x float>
- store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}load_v8i8_to_v8f32:
-; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
-; SI-NOT: bfe
-; SI-NOT: lshr
-; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
-; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
-; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
-; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
-; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
-; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
-; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
-; SI-NOT: bfe
-; SI-NOT: lshr
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-; SI: buffer_store_dword
-define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8
- %cvt = uitofp <8 x i8> %load to <8 x float>
- store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
-; SI: buffer_load_dword [[LOADREG:v[0-9]+]],
-; SI: v_add_i32_e32 [[ADD:v[0-9]+]], 2, [[LOADREG]]
-; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
-; SI: buffer_store_dword [[CONV]],
-define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 2
- %inreg = and i32 %add, 255
- %cvt = uitofp i32 %inreg to float
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
-define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %inreg = and i32 %load, 65280
- %shr = lshr i32 %inreg, 8
- %cvt = uitofp i32 %shr to float
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-
-; We don't get these ones because of the zext, but instcombine removes
-; them so it shouldn't really matter.
-define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
- %load = load i8, i8 addrspace(1)* %in, align 1
- %ext = zext i8 %load to i32
- %cvt = uitofp i32 %ext to float
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1
- %ext = zext <4 x i8> %load to <4 x i32>
- %cvt = uitofp <4 x i32> %ext to <4 x float>
- store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/cvt_flr_i32_f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cvt_flr_i32_f32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cvt_flr_i32_f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cvt_flr_i32_f32.ll (removed)
@@ -1,86 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.floor.f32(float) #1
-
-; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NOT: add
-; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
-; SI: s_endpgm
-define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
- %floor = call float @llvm.floor.f32(float %x) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
-; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
-; SI: s_endpgm
-define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
- %fadd = fadd float %x, 1.0
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
-; SI-NOT: add
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
-; SI: s_endpgm
-define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %floor = call float @llvm.floor.f32(float %x.fabs) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
-; SI-NOT: add
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
-; SI: s_endpgm
-define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
- %x.fneg = fsub float -0.000000e+00, %x
- %floor = call float @llvm.floor.f32(float %x.fneg) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
-; SI-NOT: add
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
-; SI: s_endpgm
-define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
- %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:
-; SI-NOT: v_cvt_flr_i32_f32
-; SI: v_floor_f32
-; SI: v_cvt_u32_f32_e32
-; SI: s_endpgm
-define void @no_cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
- %floor = call float @llvm.floor.f32(float %x) #1
- %cvt = fptoui float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/cvt_rpi_i32_f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cvt_rpi_i32_f32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/cvt_rpi_i32_f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/cvt_rpi_i32_f32.ll (removed)
@@ -1,83 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.floor.f32(float) #1
-
-; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
-; SI-SAFE-NOT: v_cvt_rpi_i32_f32
-; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
-; SI: s_endpgm
-define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
- %fadd = fadd float %x, 0.5
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
-; SI-SAFE-NOT: v_cvt_rpi_i32_f32
-; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
-; SI: s_endpgm
-define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %fadd = fadd float %x.fabs, 0.5
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FIXME: This doesn't work because it forms fsub 0.5, x
-; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
-; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
-; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
-; SI: s_endpgm
-define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
- %x.fneg = fsub float -0.000000e+00, %x
- %fadd = fadd float %x.fneg, 0.5
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FIXME: This doesn't work for same reason as above
-; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
-; SI-SAFE-NOT: v_cvt_rpi_i32_f32
-; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
-
-; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
-; SI-SAFE-NOT: v_cvt_flr_i32_f32
-; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
-; SI: s_endpgm
-define void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
- %x.fabs = call float @llvm.fabs.f32(float %x) #1
- %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
- %fadd = fadd float %x.fabs.fneg, 0.5
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptosi float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
-; SI-NOT: v_cvt_rpi_i32_f32
-; SI: v_add_f32
-; SI: v_floor_f32
-; SI: v_cvt_u32_f32
-; SI: s_endpgm
-define void @no_cvt_rpi_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
- %fadd = fadd float %x, 0.5
- %floor = call float @llvm.floor.f32(float %fadd) #1
- %cvt = fptoui float %floor to i32
- store i32 %cvt, i32 addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll (removed)
@@ -1,36 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; This test is for a bug in
-; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
-; the wrong type was being passed to
-; TargetLowering::getOperationAction() when checking the legality of
-; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
-
-
-; CHECK: {{^}}sint:
-; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %sint = load i32, i32 addrspace(1) * %in
- %conv = sitofp i32 %sint to float
- %0 = insertelement <4 x float> undef, float %conv, i32 0
- %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
- store <4 x float> %splat, <4 x float> addrspace(1)* %out
- ret void
-}
-
-;CHECK: {{^}}uint:
-;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %uint = load i32, i32 addrspace(1) * %in
- %conv = uitofp i32 %uint to float
- %0 = insertelement <4 x float> undef, float %conv, i32 0
- %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
- store <4 x float> %splat, <4 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/debug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/debug.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/debug.ll (original)
+++ llvm/trunk/test/CodeGen/R600/debug.ll (removed)
@@ -1,10 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-
-; Test for a crash in the custom assembly dump code.
-
-; SI: s_endpgm
-define void @test(i32 addrspace(1)* %out) {
- store i32 0, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/default-fp-mode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/default-fp-mode.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/default-fp-mode.ll (original)
+++ llvm/trunk/test/CodeGen/R600/default-fp-mode.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=FP32-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=BOTH-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=NO-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp64-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=FP32-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=BOTH-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=NO-DENORMAL -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp64-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test_kernel:
-
-; DEFAULT: FloatMode: 192
-; DEFAULT: IeeeMode: 0
-
-; FP64-DENORMAL: FloatMode: 192
-; FP64-DENORMAL: IeeeMode: 0
-
-; FP32-DENORMAL: FloatMode: 48
-; FP32-DENORMAL: IeeeMode: 0
-
-; BOTH-DENORMAL: FloatMode: 240
-; BOTH-DENORMAL: IeeeMode: 0
-
-; NO-DENORMAL: FloatMode: 0
-; NO-DENORMAL: IeeeMode: 0
-define void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind {
- store float 0.0, float addrspace(1)* %out0
- store double 0.0, double addrspace(1)* %out1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/disconnected-predset-break-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/disconnected-predset-break-bug.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/disconnected-predset-break-bug.ll (original)
+++ llvm/trunk/test/CodeGen/R600/disconnected-predset-break-bug.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; PRED_SET* instructions must be tied to any instruction that uses their
-; result. This tests that there are no instructions between the PRED_SET*
-; and the PREDICATE_BREAK in this loop.
-
-; CHECK: {{^}}loop_ge:
-; CHECK: LOOP_START_DX10
-; CHECK: ALU_PUSH_BEFORE
-; CHECK-NEXT: JUMP
-; CHECK-NEXT: LOOP_BREAK
-define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) nounwind {
-entry:
- %cmp5 = icmp sgt i32 %iterations, 0
- br i1 %cmp5, label %for.body, label %for.end
-
-for.body: ; preds = %for.body, %entry
- %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
- %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
- %i.07 = add nsw i32 %i.07.in, -1
- %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %ai.06
- store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4
- %add = add nsw i32 %ai.06, 1
- %exitcond = icmp eq i32 %add, %iterations
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end: ; preds = %for.body, %entry
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/dot4-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/dot4-folding.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/dot4-folding.ll (original)
+++ llvm/trunk/test/CodeGen/R600/dot4-folding.ll (removed)
@@ -1,27 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; Exactly one constant vector can be folded into dot4, which means exactly
-; 4 MOV instructions
-; CHECK: {{^}}main:
-; CHECK: MOV
-; CHECK: MOV
-; CHECK: MOV
-; CHECK: MOV
-; CHECK-NOT: MOV
-; CHECK-NOT: MOV
-; CHECK-NOT: MOV
-; CHECK-NOT: MOV
-
-define void @main(float addrspace(1)* %out) {
-main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %2 = call float @llvm.AMDGPU.dp4(<4 x float> %0,<4 x float> %1)
- %3 = insertelement <4 x float> undef, float %2, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %3, i32 0, i32 0)
- ret void
-}
-
-declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-attributes #1 = { readnone }
Removed: llvm/trunk/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll (removed)
@@ -1,69 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
-
-declare i32 @llvm.r600.read.tidig.x() #0
-declare void @llvm.AMDGPU.barrier.local() #1
-
-; Function Attrs: nounwind
-; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:
-; CHECK: BB0_1:
-; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
-; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
-; SI-DAG: v_add_i32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]]
-; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]]
-; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]]
-; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
-; SI-DAG: v_add_i32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]]
-; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]]
-; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]]
-; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
-
-; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:1
-; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33
-; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
-; CHECK: s_endpgm
-define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
-entry:
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #0
- %mul = shl nsw i32 %x.i, 1
- br label %for.body
-
-for.body: ; preds = %for.body, %entry
- %sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
- %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
- %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
- tail call void @llvm.AMDGPU.barrier.local() #1
- %arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02
- %tmp = load float, float addrspace(3)* %arrayidx, align 4
- %add1 = add nsw i32 %offset.02, 1
- %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1
- %tmp1 = load float, float addrspace(3)* %arrayidx2, align 4
- %add3 = add nsw i32 %offset.02, 32
- %arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3
- %tmp2 = load float, float addrspace(3)* %arrayidx4, align 4
- %add5 = add nsw i32 %offset.02, 33
- %arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5
- %tmp3 = load float, float addrspace(3)* %arrayidx6, align 4
- %add7 = add nsw i32 %offset.02, 64
- %arrayidx8 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add7
- %tmp4 = load float, float addrspace(3)* %arrayidx8, align 4
- %add9 = fadd float %tmp, %tmp1
- %add10 = fadd float %add9, %tmp2
- %add11 = fadd float %add10, %tmp3
- %add12 = fadd float %add11, %tmp4
- %add13 = fadd float %sum.03, %add12
- %inc = add nsw i32 %k.01, 1
- %add14 = add nsw i32 %offset.02, 97
- %exitcond = icmp eq i32 %inc, 8
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end: ; preds = %for.body
- %tmp5 = sext i32 %x.i to i64
- %arrayidx15 = getelementptr inbounds float, float addrspace(1)* %out, i64 %tmp5
- store float %add13, float addrspace(1)* %arrayidx15, align 4
- ret void
-}
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { noduplicate nounwind }
-attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
Removed: llvm/trunk/test/CodeGen/R600/ds_read2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_read2.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_read2.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_read2.ll (removed)
@@ -1,515 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
-
-; FIXME: We don't get cases where the address was an SGPR because we
-; get a copy to the address register for each one.
-
- at lds = addrspace(3) global [512 x float] undef, align 4
- @lds.f64 = addrspace(3) global [512 x double] undef, align 8
-
-; SI-LABEL: @simple_read2_f32
-; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:8
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2_f32(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f32_max_offset
-; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:255
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 255
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f32_too_far
-; SI-NOT ds_read2_b32
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028
-; SI: s_endpgm
-define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 257
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f32_x2
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
-; SI: s_endpgm
-define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 {
- %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
- %idx.0 = add nsw i32 %tid.x, 0
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
-
- %idx.1 = add nsw i32 %tid.x, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum.0 = fadd float %val0, %val1
-
- %idx.2 = add nsw i32 %tid.x, 11
- %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
- %val2 = load float, float addrspace(3)* %arrayidx2, align 4
-
- %idx.3 = add nsw i32 %tid.x, 27
- %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
- %val3 = load float, float addrspace(3)* %arrayidx3, align 4
- %sum.1 = fadd float %val2, %val3
-
- %sum = fadd float %sum.0, %sum.1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; Make sure there is an instruction between the two sets of reads.
-; SI-LABEL: @simple_read2_f32_x2_barrier
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
-; SI: s_barrier
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
-; SI: s_endpgm
-define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 {
- %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
- %idx.0 = add nsw i32 %tid.x, 0
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
-
- %idx.1 = add nsw i32 %tid.x, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum.0 = fadd float %val0, %val1
-
- call void @llvm.AMDGPU.barrier.local() #2
-
- %idx.2 = add nsw i32 %tid.x, 11
- %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
- %val2 = load float, float addrspace(3)* %arrayidx2, align 4
-
- %idx.3 = add nsw i32 %tid.x, 27
- %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
- %val3 = load float, float addrspace(3)* %arrayidx3, align 4
- %sum.1 = fadd float %val2, %val3
-
- %sum = fadd float %sum.0, %sum.1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; For some reason adding something to the base address for the first
-; element results in only folding the inner pair.
-
-; SI-LABEL: @simple_read2_f32_x2_nonzero_base
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:2 offset1:8
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
-; SI: s_endpgm
-define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 {
- %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
- %idx.0 = add nsw i32 %tid.x, 2
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
-
- %idx.1 = add nsw i32 %tid.x, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum.0 = fadd float %val0, %val1
-
- %idx.2 = add nsw i32 %tid.x, 11
- %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
- %val2 = load float, float addrspace(3)* %arrayidx2, align 4
-
- %idx.3 = add nsw i32 %tid.x, 27
- %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
- %val3 = load float, float addrspace(3)* %arrayidx3, align 4
- %sum.1 = fadd float %val2, %val3
-
- %sum = fadd float %sum.0, %sum.1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; Be careful of vectors of pointers. We don't know if the 2 pointers
-; in the vectors are really the same base, so this is not safe to
-; merge.
-; Base pointers come from different subregister of same super
-; register. We can't safely merge this.
-
-; SI-LABEL: @read2_ptr_is_subreg_arg_f32
-; SI-NOT: ds_read2_b32
-; SI: ds_read_b32
-; SI: ds_read_b32
-; SI: s_endpgm
-define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
- %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
- %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
- %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
- %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
- %val0 = load float, float addrspace(3)* %gep.0, align 4
- %val1 = load float, float addrspace(3)* %gep.1, align 4
- %add.x = add nsw i32 %x.i, 8
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; Apply a constant scalar offset after the pointer vector extract. We
-; are rejecting merges that have the same, constant 0 offset, so make
-; sure we are really rejecting it because of the different
-; subregisters.
-
-; SI-LABEL: @read2_ptr_is_subreg_arg_offset_f32
-; SI-NOT: ds_read2_b32
-; SI: ds_read_b32
-; SI: ds_read_b32
-; SI: s_endpgm
-define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
- %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
- %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
- %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
- %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
-
- ; Apply an additional offset after the vector that will be more obviously folded.
- %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8
-
- %val0 = load float, float addrspace(3)* %gep.0, align 4
- %val1 = load float, float addrspace(3)* %gep.1.offset, align 4
- %add.x = add nsw i32 %x.i, 8
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; We should be able to merge in this case, but probably not worth the effort.
-; SI-NOT: ds_read2_b32
-; SI: ds_read_b32
-; SI: ds_read_b32
-; SI: s_endpgm
-define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %ptr.0 = insertelement <2 x [512 x float] addrspace(3)*> undef, [512 x float] addrspace(3)* @lds, i32 0
- %ptr.1 = insertelement <2 x [512 x float] addrspace(3)*> %ptr.0, [512 x float] addrspace(3)* @lds, i32 1
- %x.i.v.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
- %x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1
- %idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>
- %gep = getelementptr inbounds [512 x float], <2 x [512 x float] addrspace(3)*> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx
- %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
- %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
- %val0 = load float, float addrspace(3)* %gep.0, align 4
- %val1 = load float, float addrspace(3)* %gep.1, align 4
- %add.x = add nsw i32 %x.i, 8
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f32_volatile_0
-; SI-NOT ds_read2_b32
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
-; SI: s_endpgm
-define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load volatile float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f32_volatile_1
-; SI-NOT ds_read2_b32
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
-; SI: s_endpgm
-define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load volatile float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; Can't fold since not correctly aligned.
-; XXX: This isn't really testing anything useful now. I think CI
-; allows unaligned LDS accesses, which would be a problem here.
-; SI-LABEL: @unaligned_read2_f32
-; SI-NOT: ds_read2_b32
-; SI: s_endpgm
-define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 1
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 1
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @misaligned_2_simple_read2_f32
-; SI-NOT: ds_read2_b32
-; SI: s_endpgm
-define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 2
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 2
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2_f64
-; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}}
-; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
-; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2_f64(double addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; SI-LABEL: @simple_read2_f64_max_offset
-; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:255
-; SI: s_endpgm
-define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 255
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; SI-LABEL: @simple_read2_f64_too_far
-; SI-NOT ds_read2_b64
-; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
-; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:2056
-; SI: s_endpgm
-define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 257
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; Alignment only 4
-; SI-LABEL: @misaligned_read2_f64
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:1
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15
-; SI: s_endpgm
-define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 7
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 4
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 4
- ret void
-}
-
- at foo = addrspace(3) global [4 x i32] undef, align 4
-
-; SI-LABEL: @load_constant_adjacent_offsets
-; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
-define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) {
- %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
- %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
- %sum = add i32 %val0, %val1
- store i32 %sum, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: @load_constant_disjoint_offsets
-; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:2
-define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) {
- %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
- %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
- %sum = add i32 %val0, %val1
- store i32 %sum, i32 addrspace(1)* %out, align 4
- ret void
-}
-
- at bar = addrspace(3) global [4 x i64] undef, align 4
-
-; SI-LABEL: @load_misaligned64_constant_offsets
-; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3
-define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
- %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
- %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
- %sum = add i64 %val0, %val1
- store i64 %sum, i64 addrspace(1)* %out, align 8
- ret void
-}
-
- at bar.large = addrspace(3) global [4096 x i64] undef, align 4
-
-; SI-LABEL: @load_misaligned64_constant_large_offsets
-; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}}
-; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000
-; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset1:1
-; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset1:1
-; SI: s_endpgm
-define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) {
- %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
- %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
- %sum = add i64 %val0, %val1
- store i64 %sum, i64 addrspace(1)* %out, align 8
- ret void
-}
-
- at sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
- at sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
-
-define void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb) #0 {
- %x.i = tail call i32 @llvm.r600.read.tgid.x() #1
- %y.i = tail call i32 @llvm.r600.read.tidig.y() #1
- %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
- %tmp16 = load float, float addrspace(3)* %arrayidx44, align 4
- %add47 = add nsw i32 %x.i, 1
- %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
- %tmp17 = load float, float addrspace(3)* %arrayidx48, align 4
- %add51 = add nsw i32 %x.i, 16
- %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
- %tmp18 = load float, float addrspace(3)* %arrayidx52, align 4
- %add55 = add nsw i32 %x.i, 17
- %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
- %tmp19 = load float, float addrspace(3)* %arrayidx56, align 4
- %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
- %tmp20 = load float, float addrspace(3)* %arrayidx60, align 4
- %add63 = add nsw i32 %y.i, 1
- %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
- %tmp21 = load float, float addrspace(3)* %arrayidx64, align 4
- %add67 = add nsw i32 %y.i, 32
- %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
- %tmp22 = load float, float addrspace(3)* %arrayidx68, align 4
- %add71 = add nsw i32 %y.i, 33
- %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
- %tmp23 = load float, float addrspace(3)* %arrayidx72, align 4
- %add75 = add nsw i32 %y.i, 64
- %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
- %tmp24 = load float, float addrspace(3)* %arrayidx76, align 4
- %add79 = add nsw i32 %y.i, 65
- %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
- %tmp25 = load float, float addrspace(3)* %arrayidx80, align 4
- %sum.0 = fadd float %tmp16, %tmp17
- %sum.1 = fadd float %sum.0, %tmp18
- %sum.2 = fadd float %sum.1, %tmp19
- %sum.3 = fadd float %sum.2, %tmp20
- %sum.4 = fadd float %sum.3, %tmp21
- %sum.5 = fadd float %sum.4, %tmp22
- %sum.6 = fadd float %sum.5, %tmp23
- %sum.7 = fadd float %sum.6, %tmp24
- %sum.8 = fadd float %sum.7, %tmp25
- store float %sum.8, float addrspace(1)* %C, align 4
- ret void
-}
-
-define void @misaligned_read2_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(3)* %in) #0 {
- %load = load <2 x i32>, <2 x i32> addrspace(3)* %in, align 4
- store <2 x i32> %load, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-define void @misaligned_read2_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) #0 {
- %load = load i64, i64 addrspace(3)* %in, align 4
- store i64 %load, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.y() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.y() #1
-
-; Function Attrs: noduplicate nounwind
-declare void @llvm.AMDGPU.barrier.local() #2
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { noduplicate nounwind }
Removed: llvm/trunk/test/CodeGen/R600/ds_read2_offset_order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_read2_offset_order.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_read2_offset_order.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_read2_offset_order.ll (removed)
@@ -1,45 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
-
-; XFAIL: *
-
- at lds = addrspace(3) global [512 x float] undef, align 4
-
-; SI-LABEL: {{^}}offset_order:
-
-; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:56
-; SI: ds_read2st64_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:0 offset1:4
-; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3
-; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:1
-
-define void @offset_order(float addrspace(1)* %out) {
-entry:
- %ptr0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 0
- %val0 = load float, float addrspace(3)* %ptr0
-
- %ptr1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 256
- %val1 = load float, float addrspace(3)* %ptr1
- %add1 = fadd float %val0, %val1
-
- %ptr2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 3
- %val2 = load float, float addrspace(3)* %ptr2
- %add2 = fadd float %add1, %val2
-
- %ptr3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 2
- %val3 = load float, float addrspace(3)* %ptr3
- %add3 = fadd float %add2, %val3
-
- %ptr4 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 12
- %val4 = load float, float addrspace(3)* %ptr4
- %add4 = fadd float %add3, %val4
-
- %ptr5 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 14
- %val5 = load float, float addrspace(3)* %ptr5
- %add5 = fadd float %add4, %val5
-
- %ptr6 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 11
- %val6 = load float, float addrspace(3)* %ptr6
- %add6 = fadd float %add5, %val6
- store float %add6, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ds_read2st64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_read2st64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_read2st64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_read2st64.ll (removed)
@@ -1,272 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
-
- at lds = addrspace(3) global [512 x float] undef, align 4
- at lds.f64 = addrspace(3) global [512 x double] undef, align 8
-
-
-; SI-LABEL: @simple_read2st64_f32_0_1
-; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 64
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f32_1_2
-; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x.1 = add nsw i32 %x.i, 128
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f32_max_offset
-; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x.1 = add nsw i32 %x.i, 16320
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f32_over_max_offset
-; SI-NOT: ds_read2st64_b32
-; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
-; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
-; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
-; SI: s_endpgm
-define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x.1 = add nsw i32 %x.i, 16384
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @odd_invalid_read2st64_f32_0
-; SI-NOT: ds_read2st64_b32
-; SI: s_endpgm
-define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 63
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @odd_invalid_read2st64_f32_1
-; SI-NOT: ds_read2st64_b32
-; SI: s_endpgm
-define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
- %val0 = load float, float addrspace(3)* %arrayidx0, align 4
- %add.x.1 = add nsw i32 %x.i, 127
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
- %val1 = load float, float addrspace(3)* %arrayidx1, align 4
- %sum = fadd float %val0, %val1
- %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
- store float %sum, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f64_0_1
-; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 64
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f64_1_2
-; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x.1 = add nsw i32 %x.i, 128
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; Alignment only
-
-; SI-LABEL: @misaligned_read2st64_f64
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:1
-; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129
-; SI: s_endpgm
-define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 64
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 4
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff
-; SI-LABEL: @simple_read2st64_f64_max_offset
-; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127
-; SI: s_waitcnt lgkmcnt(0)
-; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT]]
-; SI: s_endpgm
-define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 256
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x.1 = add nsw i32 %x.i, 8128
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; SI-LABEL: @simple_read2st64_f64_over_max_offset
-; SI-NOT: ds_read2st64_b64
-; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
-; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512
-; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]]
-; SI: s_endpgm
-define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x.1 = add nsw i32 %x.i, 8192
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; SI-LABEL: @invalid_read2st64_f64_odd_offset
-; SI-NOT: ds_read2st64_b64
-; SI: s_endpgm
-define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %add.x.0 = add nsw i32 %x.i, 64
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x.1 = add nsw i32 %x.i, 8129
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 8
- ret void
-}
-
-; The stride of 8 elements is 8 * 8 bytes. We need to make sure the
-; stride in elements, not bytes, is a multiple of 64.
-
-; SI-LABEL: @byte_size_only_divisible_64_read2_f64
-; SI-NOT: ds_read2st_b64
-; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:8
-; SI: s_endpgm
-define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
- %val0 = load double, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
- %val1 = load double, double addrspace(3)* %arrayidx1, align 8
- %sum = fadd double %val0, %val1
- %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
- store double %sum, double addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.y() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.y() #1
-
-; Function Attrs: noduplicate nounwind
-declare void @llvm.AMDGPU.barrier.local() #2
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { noduplicate nounwind }
Removed: llvm/trunk/test/CodeGen/R600/ds_write2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_write2.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_write2.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_write2.ll (removed)
@@ -1,425 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -strict-whitespace -check-prefix=SI %s
-
- at lds = addrspace(3) global [512 x float] undef, align 4
- at lds.f64 = addrspace(3) global [512 x double] undef, align 8
-
-
-; SI-LABEL: @simple_write2_one_val_f32
-; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %val = load float, float addrspace(1)* %in.gep, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f32
-; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
- %val0 = load float, float addrspace(1)* %in.gep.0, align 4
- %val1 = load float, float addrspace(1)* %in.gep.1, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f32_volatile_0
-; SI-NOT: ds_write2_b32
-; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}}
-; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32
-; SI: s_endpgm
-define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store volatile float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f32_volatile_1
-; SI-NOT: ds_write2_b32
-; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}}
-; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32
-; SI: s_endpgm
-define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store volatile float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; 2 data subregisters from different super registers.
-; SI-LABEL: @simple_write2_two_val_subreg2_mixed_f32
-; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}}
-; SI: buffer_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}}
-; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1
- %val0 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8
- %val1 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8
- %val0.0 = extractelement <2 x float> %val0, i32 0
- %val1.1 = extractelement <2 x float> %val1, i32 1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0.0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1.1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_subreg2_f32
-; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i
- %val = load <2 x float>, <2 x float> addrspace(1)* %in.gep, align 8
- %val0 = extractelement <2 x float> %val, i32 0
- %val1 = extractelement <2 x float> %val, i32 1
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_subreg4_f32
-; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 %x.i
- %val = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 16
- %val0 = extractelement <4 x float> %val, i32 0
- %val1 = extractelement <4 x float> %val, i32 3
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_max_offset_f32
-; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
-; SI: s_endpgm
-define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
- %val0 = load float, float addrspace(1)* %in.gep.0, align 4
- %val1 = load float, float addrspace(1)* %in.gep.1, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 255
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_too_far_f32
-; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}
-; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028
-; SI: s_endpgm
-define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 257
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f32_x2
-; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8
-; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27
-; SI: s_endpgm
-define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
- %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
-
- %idx.0 = add nsw i32 %tid.x, 0
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
- store float %val0, float addrspace(3)* %arrayidx0, align 4
-
- %idx.1 = add nsw i32 %tid.x, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
- store float %val1, float addrspace(3)* %arrayidx1, align 4
-
- %idx.2 = add nsw i32 %tid.x, 11
- %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
- store float %val0, float addrspace(3)* %arrayidx2, align 4
-
- %idx.3 = add nsw i32 %tid.x, 27
- %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
- store float %val1, float addrspace(3)* %arrayidx3, align 4
-
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f32_x2_nonzero_base
-; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8
-; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27
-; SI: s_endpgm
-define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 {
- %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
-
- %idx.0 = add nsw i32 %tid.x, 3
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
- store float %val0, float addrspace(3)* %arrayidx0, align 4
-
- %idx.1 = add nsw i32 %tid.x, 8
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
- store float %val1, float addrspace(3)* %arrayidx1, align 4
-
- %idx.2 = add nsw i32 %tid.x, 11
- %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
- store float %val0, float addrspace(3)* %arrayidx2, align 4
-
- %idx.3 = add nsw i32 %tid.x, 27
- %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
- store float %val1, float addrspace(3)* %arrayidx3, align 4
-
- ret void
-}
-
-; SI-LABEL: @write2_ptr_subreg_arg_two_val_f32
-; SI-NOT: ds_write2_b32
-; SI: ds_write_b32
-; SI: ds_write_b32
-; SI: s_endpgm
-define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
- %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
- %val0 = load float, float addrspace(1)* %in0.gep, align 4
- %val1 = load float, float addrspace(1)* %in1.gep, align 4
-
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
- %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
- %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
- %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
- %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
-
- ; Apply an additional offset after the vector that will be more obviously folded.
- %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8
- store float %val0, float addrspace(3)* %gep.0, align 4
-
- %add.x = add nsw i32 %x.i, 8
- store float %val1, float addrspace(3)* %gep.1.offset, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_one_val_f64
-; SI: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]],
-; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
- %val = load double, double addrspace(1)* %in.gep, align 8
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- store double %val, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- store double %val, double addrspace(3)* %arrayidx1, align 8
- ret void
-}
-
-; SI-LABEL: @misaligned_simple_write2_one_val_f64
-; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:1
-; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15
-; SI: s_endpgm
-define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
- %val = load double, double addrspace(1)* %in.gep, align 8
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
- store double %val, double addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 7
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
- store double %val, double addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2_two_val_f64
-; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
-; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
-; SI: s_endpgm
-define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1
- %val0 = load double, double addrspace(1)* %in.gep.0, align 8
- %val1 = load double, double addrspace(1)* %in.gep.1, align 8
- %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
- store double %val0, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
- store double %val1, double addrspace(3)* %arrayidx1, align 8
- ret void
-}
-
- at foo = addrspace(3) global [4 x i32] undef, align 4
-
-; SI-LABEL: @store_constant_adjacent_offsets
-; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
-define void @store_constant_adjacent_offsets() {
- store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
- store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
- ret void
-}
-
-; SI-LABEL: @store_constant_disjoint_offsets
-; SI-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b{{$}}
-; SI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], [[VAL]], [[VAL]] offset1:2
-define void @store_constant_disjoint_offsets() {
- store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
- store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
- ret void
-}
-
- at bar = addrspace(3) global [4 x i64] undef, align 4
-
-; SI-LABEL: @store_misaligned64_constant_offsets
-; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
-; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
-; SI: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
-define void @store_misaligned64_constant_offsets() {
- store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
- store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
- ret void
-}
-
- at bar.large = addrspace(3) global [4096 x i64] undef, align 4
-
-; SI-LABEL: @store_misaligned64_constant_large_offsets
-; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}}
-; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000{{$}}
-; SI-DAG: ds_write2_b32 [[BASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
-; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
-; SI: s_endpgm
-define void @store_misaligned64_constant_large_offsets() {
- store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
- store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
- ret void
-}
-
- at sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
- at sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
-
-define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tgid.x() #1
- %y.i = tail call i32 @llvm.r600.read.tidig.y() #1
- %val = load float, float addrspace(1)* %in
- %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
- store float %val, float addrspace(3)* %arrayidx44, align 4
- %add47 = add nsw i32 %x.i, 1
- %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
- store float %val, float addrspace(3)* %arrayidx48, align 4
- %add51 = add nsw i32 %x.i, 16
- %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
- store float %val, float addrspace(3)* %arrayidx52, align 4
- %add55 = add nsw i32 %x.i, 17
- %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
- store float %val, float addrspace(3)* %arrayidx56, align 4
- %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
- store float %val, float addrspace(3)* %arrayidx60, align 4
- %add63 = add nsw i32 %y.i, 1
- %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
- store float %val, float addrspace(3)* %arrayidx64, align 4
- %add67 = add nsw i32 %y.i, 32
- %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
- store float %val, float addrspace(3)* %arrayidx68, align 4
- %add71 = add nsw i32 %y.i, 33
- %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
- store float %val, float addrspace(3)* %arrayidx72, align 4
- %add75 = add nsw i32 %y.i, 64
- %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
- store float %val, float addrspace(3)* %arrayidx76, align 4
- %add79 = add nsw i32 %y.i, 65
- %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
- store float %val, float addrspace(3)* %arrayidx80, align 4
- ret void
-}
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.y() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.y() #1
-
-; Function Attrs: noduplicate nounwind
-declare void @llvm.AMDGPU.barrier.local() #2
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { noduplicate nounwind }
Removed: llvm/trunk/test/CodeGen/R600/ds_write2st64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_write2st64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_write2st64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_write2st64.ll (removed)
@@ -1,119 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
-
-
- at lds = addrspace(3) global [512 x float] undef, align 4
-
-
-; SI-LABEL: @simple_write2st64_one_val_f32_0_1
-; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1
-; SI: s_endpgm
-define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %val = load float, float addrspace(1)* %in.gep, align 4
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
- store float %val, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 64
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
- store float %val, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2st64_two_val_f32_2_5
-; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
-; SI: s_endpgm
-define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
- %val0 = load float, float addrspace(1)* %in.gep.0, align 4
- %val1 = load float, float addrspace(1)* %in.gep.1, align 4
- %add.x.0 = add nsw i32 %x.i, 128
- %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x.1 = add nsw i32 %x.i, 320
- %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2st64_two_val_max_offset_f32
-; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
-; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
-; SI: s_endpgm
-define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
- %val0 = load float, float addrspace(1)* %in.gep.0, align 4
- %val1 = load float, float addrspace(1)* %in.gep.1, align 4
- %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
- store float %val0, float addrspace(3)* %arrayidx0, align 4
- %add.x = add nsw i32 %x.i, 16320
- %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
- store float %val1, float addrspace(3)* %arrayidx1, align 4
- ret void
-}
-
-; SI-LABEL: @simple_write2st64_two_val_max_offset_f64
-; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
-; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]],
-; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
-; SI: s_endpgm
-define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i
- %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1
- %val0 = load double, double addrspace(1)* %in.gep.0, align 8
- %val1 = load double, double addrspace(1)* %in.gep.1, align 8
- %add.x.0 = add nsw i32 %x.i, 256
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0
- store double %val0, double addrspace(3)* %arrayidx0, align 8
- %add.x.1 = add nsw i32 %x.i, 8128
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1
- store double %val1, double addrspace(3)* %arrayidx1, align 8
- ret void
-}
-
-; SI-LABEL: @byte_size_only_divisible_64_write2st64_f64
-; SI-NOT: ds_write2st64_b64
-; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8
-; SI: s_endpgm
-define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
- %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
- %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i
- %val = load double, double addrspace(1)* %in.gep, align 8
- %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
- store double %val, double addrspace(3)* %arrayidx0, align 8
- %add.x = add nsw i32 %x.i, 8
- %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
- store double %val, double addrspace(3)* %arrayidx1, align 8
- ret void
-}
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tgid.y() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.r600.read.tidig.y() #1
-
-; Function Attrs: noduplicate nounwind
-declare void @llvm.AMDGPU.barrier.local() #2
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { noduplicate nounwind }
Removed: llvm/trunk/test/CodeGen/R600/elf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/elf.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/elf.ll (original)
+++ llvm/trunk/test/CodeGen/R600/elf.ll (removed)
@@ -1,34 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
-; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
-
-; Test that we don't try to produce a COFF file on windows
-; RUN: llc < %s -mtriple=amdgcn-pc-mingw -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s
-
-; ELF: Format: ELF32
-; ELF: Name: .AMDGPU.config
-; ELF: Type: SHT_PROGBITS
-
-; ELF: Symbol {
-; ELF: Name: test
-; ELF: Binding: Global
-
-; CONFIG: .section .AMDGPU.config
-; CONFIG-NEXT: .long 45096
-; TYPICAL-NEXT: .long 0
-; TONGA-NEXT: .long 576
-; CONFIG: .align 256
-; CONFIG: test:
-define void @test(i32 %p) #0 {
- %i = add i32 %p, 2
- %r = bitcast i32 %i to float
- call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
- ret void
-}
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { "ShaderType"="0" } ; Pixel Shader
Removed: llvm/trunk/test/CodeGen/R600/elf.r600.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/elf.r600.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/elf.r600.ll (original)
+++ llvm/trunk/test/CodeGen/R600/elf.r600.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s
-
-; ELF: Format: ELF32
-; ELF: Name: .AMDGPU.config
-
-; CONFIG: .section .AMDGPU.config
-; CONFIG-NEXT: .long 166100
-; CONFIG-NEXT: .long 2
-; CONFIG-NEXT: .long 165900
-; CONFIG-NEXT: .long 0
-define void @test(float addrspace(1)* %out, i32 %p) {
- %i = add i32 %p, 2
- %r = bitcast i32 %i to float
- store float %r, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/empty-function.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/empty-function.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/empty-function.ll (original)
+++ llvm/trunk/test/CodeGen/R600/empty-function.ll (removed)
@@ -1,21 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; Make sure we don't assert on empty functions
-
-; SI: .text
-; SI-LABEL: {{^}}empty_function_ret:
-; SI: s_endpgm
-; SI: codeLenInByte = 4
-define void @empty_function_ret() #0 {
- ret void
-}
-
-; SI: .text
-; SI-LABEL: {{^}}empty_function_unreachable:
-; SI: codeLenInByte = 0
-define void @empty_function_unreachable() #0 {
- unreachable
-}
-
-attributes #0 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/endcf-loop-header.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/endcf-loop-header.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/endcf-loop-header.ll (original)
+++ llvm/trunk/test/CodeGen/R600/endcf-loop-header.ll (removed)
@@ -1,34 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
-
-; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
-; loop block. This intrinsic will be lowered to s_or_b64 by the code
-; generator.
-
-; CHECK-LABEL: {{^}}test:
-
-; This is was lowered from the llvm.SI.end.cf intrinsic:
-; CHECK: s_or_b64 exec, exec
-
-; CHECK: [[LOOP_LABEL:[0-9A-Za-z_]+]]: ; %loop{{$}}
-; CHECK-NOT: s_or_b64 exec, exec
-; CHECK: s_cbranch_execnz [[LOOP_LABEL]]
-define void @test(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %tmp0 = icmp eq i32 %cond, 0
- br i1 %tmp0, label %if, label %loop
-
-if:
- store i32 0, i32 addrspace(1)* %out
- br label %loop
-
-loop:
- %tmp1 = phi i32 [0, %entry], [0, %if], [%inc, %loop]
- %inc = add i32 %tmp1, %cond
- %tmp2 = icmp ugt i32 %inc, 10
- br i1 %tmp2, label %done, label %loop
-
-done:
- %tmp3 = getelementptr i32, i32 addrspace(1)* %out, i64 1
- store i32 %inc, i32 addrspace(1)* %tmp3
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/extload-private.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extload-private.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extload-private.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extload-private.ll (removed)
@@ -1,46 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}load_i8_sext_private:
-; SI: buffer_load_sbyte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
-define void @load_i8_sext_private(i32 addrspace(1)* %out) {
-entry:
- %tmp0 = alloca i8
- %tmp1 = load i8, i8* %tmp0
- %tmp2 = sext i8 %tmp1 to i32
- store i32 %tmp2, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}load_i8_zext_private:
-; SI: buffer_load_ubyte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
-define void @load_i8_zext_private(i32 addrspace(1)* %out) {
-entry:
- %tmp0 = alloca i8
- %tmp1 = load i8, i8* %tmp0
- %tmp2 = zext i8 %tmp1 to i32
- store i32 %tmp2, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}load_i16_sext_private:
-; SI: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
-define void @load_i16_sext_private(i32 addrspace(1)* %out) {
-entry:
- %tmp0 = alloca i16
- %tmp1 = load i16, i16* %tmp0
- %tmp2 = sext i16 %tmp1 to i32
- store i32 %tmp2, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}load_i16_zext_private:
-; SI: buffer_load_ushort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
-define void @load_i16_zext_private(i32 addrspace(1)* %out) {
-entry:
- %tmp0 = alloca i16
- %tmp1 = load i16, i16* %tmp0
- %tmp2 = zext i16 %tmp1 to i32
- store i32 %tmp2, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extload.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extload.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extload.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}anyext_load_i8:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
-; EG: VTX_READ_32 [[VAL]]
-
-define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind {
- %cast = bitcast i8 addrspace(1)* %src to i32 addrspace(1)*
- %load = load i32, i32 addrspace(1)* %cast, align 1
- %x = bitcast i32 %load to <4 x i8>
- %castOut = bitcast i8 addrspace(1)* %out to <4 x i8> addrspace(1)*
- store <4 x i8> %x, <4 x i8> addrspace(1)* %castOut, align 1
- ret void
-}
-
-; FUNC-LABEL: {{^}}anyext_load_i16:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
-; EG: VTX_READ_32 [[VAL]]
-
-define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind {
- %cast = bitcast i16 addrspace(1)* %src to i32 addrspace(1)*
- %load = load i32, i32 addrspace(1)* %cast, align 1
- %x = bitcast i32 %load to <2 x i16>
- %castOut = bitcast i16 addrspace(1)* %out to <2 x i16> addrspace(1)*
- store <2 x i16> %x, <2 x i16> addrspace(1)* %castOut, align 1
- ret void
-}
-
-; FUNC-LABEL: {{^}}anyext_load_lds_i8:
-; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
-; EG: LDS_WRITE * [[VAL]]
-define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind {
- %cast = bitcast i8 addrspace(3)* %src to i32 addrspace(3)*
- %load = load i32, i32 addrspace(3)* %cast, align 1
- %x = bitcast i32 %load to <4 x i8>
- %castOut = bitcast i8 addrspace(3)* %out to <4 x i8> addrspace(3)*
- store <4 x i8> %x, <4 x i8> addrspace(3)* %castOut, align 1
- ret void
-}
-
-; FUNC-LABEL: {{^}}anyext_load_lds_i16:
-; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
-; EG: LDS_WRITE * [[VAL]]
-define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind {
- %cast = bitcast i16 addrspace(3)* %src to i32 addrspace(3)*
- %load = load i32, i32 addrspace(3)* %cast, align 1
- %x = bitcast i32 %load to <2 x i16>
- %castOut = bitcast i16 addrspace(3)* %out to <2 x i16> addrspace(3)*
- store <2 x i16> %x, <2 x i16> addrspace(3)* %castOut, align 1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}extract_vector_elt_v2i16:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_store_short
-; SI: buffer_store_short
-define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) nounwind {
- %p0 = extractelement <2 x i16> %foo, i32 0
- %p1 = extractelement <2 x i16> %foo, i32 1
- %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
- store i16 %p1, i16 addrspace(1)* %out, align 2
- store i16 %p0, i16 addrspace(1)* %out1, align 2
- ret void
-}
-
-; FUNC-LABEL: {{^}}extract_vector_elt_v4i16:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_store_short
-; SI: buffer_store_short
-define void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) nounwind {
- %p0 = extractelement <4 x i16> %foo, i32 0
- %p1 = extractelement <4 x i16> %foo, i32 2
- %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1
- store i16 %p1, i16 addrspace(1)* %out, align 2
- store i16 %p0, i16 addrspace(1)* %out1, align 2
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fabs.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fabs.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fabs.f64.ll (removed)
@@ -1,97 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-
-declare double @fabs(double) readnone
-declare double @llvm.fabs.f64(double) readnone
-declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
-declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
-
-; FUNC-LABEL: {{^}}v_fabs_f64:
-; SI: v_and_b32
-; SI: s_endpgm
-define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %tidext = sext i32 %tid to i64
- %gep = getelementptr double, double addrspace(1)* %in, i64 %tidext
- %val = load double, double addrspace(1)* %gep, align 8
- %fabs = call double @llvm.fabs.f64(double %val)
- store double %fabs, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_f64:
-; SI: v_and_b32
-; SI-NOT: v_and_b32
-; SI: s_endpgm
-define void @fabs_f64(double addrspace(1)* %out, double %in) {
- %fabs = call double @llvm.fabs.f64(double %in)
- store double %fabs, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_v2f64:
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: s_endpgm
-define void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
- %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
- store <2 x double> %fabs, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_v4f64:
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: v_and_b32
-; SI: s_endpgm
-define void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
- %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
- store <4 x double> %fabs, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fabs_fold_f64:
-; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-NOT: and
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
-; SI: s_endpgm
-define void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
- %fabs = call double @llvm.fabs.f64(double %in0)
- %fmul = fmul double %fabs, %in1
- store double %fmul, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fabs_fn_fold_f64:
-; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-NOT: and
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
-; SI: s_endpgm
-define void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
- %fabs = call double @fabs(double %in0)
- %fmul = fmul double %fabs, %in1
- store double %fmul, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_free_f64:
-; SI: v_and_b32
-; SI: s_endpgm
-define void @fabs_free_f64(double addrspace(1)* %out, i64 %in) {
- %bc= bitcast i64 %in to double
- %fabs = call double @llvm.fabs.f64(double %bc)
- store double %fabs, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_fn_free_f64:
-; SI: v_and_b32
-; SI: s_endpgm
-define void @fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
- %bc= bitcast i64 %in to double
- %fabs = call double @fabs(double %bc)
- store double %fabs, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fabs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fabs.ll (removed)
@@ -1,101 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-
-; DAGCombiner will transform:
-; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
-; unless isFabsFree returns true
-
-; FUNC-LABEL: {{^}}fabs_fn_free:
-; R600-NOT: AND
-; R600: |PV.{{[XYZW]}}|
-
-; GCN: v_and_b32
-
-define void @fabs_fn_free(float addrspace(1)* %out, i32 %in) {
- %bc= bitcast i32 %in to float
- %fabs = call float @fabs(float %bc)
- store float %fabs, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_free:
-; R600-NOT: AND
-; R600: |PV.{{[XYZW]}}|
-
-; GCN: v_and_b32
-
-define void @fabs_free(float addrspace(1)* %out, i32 %in) {
- %bc= bitcast i32 %in to float
- %fabs = call float @llvm.fabs.f32(float %bc)
- store float %fabs, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_f32:
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-
-; GCN: v_and_b32
-define void @fabs_f32(float addrspace(1)* %out, float %in) {
- %fabs = call float @llvm.fabs.f32(float %in)
- store float %fabs, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_v2f32:
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-
-; GCN: v_and_b32
-; GCN: v_and_b32
-define void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
- %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
- store <2 x float> %fabs, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fabs_v4f32:
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-
-; GCN: v_and_b32
-; GCN: v_and_b32
-; GCN: v_and_b32
-; GCN: v_and_b32
-define void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
- %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
- store <4 x float> %fabs, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}fabs_fn_fold:
-; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
-; GCN-NOT: and
-; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
-define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
- %fabs = call float @fabs(float %in0)
- %fmul = fmul float %fabs, %in1
- store float %fmul, float addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}fabs_fold:
-; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
-; GCN-NOT: and
-; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
-define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
- %fabs = call float @llvm.fabs.f32(float %in0)
- %fmul = fmul float %fabs, %in1
- store float %fmul, float addrspace(1)* %out
- ret void
-}
-
-declare float @fabs(float) readnone
-declare float @llvm.fabs.f32(float) readnone
-declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
Removed: llvm/trunk/test/CodeGen/R600/fadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fadd.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fadd.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fadd.ll (removed)
@@ -1,64 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-
-; FUNC-LABEL: {{^}}fadd_f32:
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
-; SI: v_add_f32
-define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) {
- %add = fadd float %a, %b
- store float %add, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fadd_v2f32:
-; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
-; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
-; SI: v_add_f32
-; SI: v_add_f32
-define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
- %add = fadd <2 x float> %a, %b
- store <2 x float> %add, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}fadd_v4f32:
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
- %b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
- %result = fadd <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: {{^}}fadd_v8f32:
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; R600: ADD
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-define void @fadd_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) {
- %add = fadd <8 x float> %a, %b
- store <8 x float> %add, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fadd64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fadd64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fadd64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fadd64.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; CHECK: {{^}}fadd_f64:
-; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}
-
-define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fadd double %r0, %r1
- store double %r2, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fceil.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fceil.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fceil.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fceil.ll (removed)
@@ -1,132 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.ceil.f32(float) nounwind readnone
-declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone
-declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone
-declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
-declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
-declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
-
-; FUNC-LABEL: {{^}}fceil_f32:
-; SI: v_ceil_f32_e32
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
-; EG: CEIL {{\*? *}}[[RESULT]]
-define void @fceil_f32(float addrspace(1)* %out, float %x) {
- %y = call float @llvm.ceil.f32(float %x) nounwind readnone
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v2f32:
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: CEIL {{\*? *}}[[RESULT]]
-; EG: CEIL {{\*? *}}[[RESULT]]
-define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) {
- %y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone
- store <2 x float> %y, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v3f32:
-; FIXME-SI: v_ceil_f32_e32
-; FIXME-SI: v_ceil_f32_e32
-; FIXME-SI: v_ceil_f32_e32
-; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) {
- %y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone
- store <3 x float> %y, <3 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v4f32:
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
-; EG: CEIL {{\*? *}}[[RESULT]]
-; EG: CEIL {{\*? *}}[[RESULT]]
-; EG: CEIL {{\*? *}}[[RESULT]]
-; EG: CEIL {{\*? *}}[[RESULT]]
-define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) {
- %y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone
- store <4 x float> %y, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v8f32:
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) {
- %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
- store <8 x float> %y, <8 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v16f32:
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; SI: v_ceil_f32_e32
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}}
-; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}}
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
-; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
-define void @fceil_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) {
- %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
- store <16 x float> %y, <16 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fceil64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fceil64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fceil64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fceil64.ll (removed)
@@ -1,105 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare double @llvm.ceil.f64(double) nounwind readnone
-declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
-declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
-declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
-declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
-declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
-
-; FUNC-LABEL: {{^}}fceil_f64:
-; CI: v_ceil_f64_e32
-; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
-; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
-; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
-; SI: s_lshr_b64
-; SI: s_not_b64
-; SI: s_and_b64
-; SI: cmp_gt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI: cmp_lt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI-DAG: v_cmp_lt_f64
-; SI-DAG: v_cmp_lg_f64
-; SI: s_and_b64
-; SI: v_cndmask_b32
-; SI: v_cndmask_b32
-; SI: v_add_f64
-; SI: s_endpgm
-define void @fceil_f64(double addrspace(1)* %out, double %x) {
- %y = call double @llvm.ceil.f64(double %x) nounwind readnone
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v2f64:
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-define void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
- %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
- store <2 x double> %y, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FIXME-FUNC-LABEL: {{^}}fceil_v3f64:
-; FIXME-CI: v_ceil_f64_e32
-; FIXME-CI: v_ceil_f64_e32
-; FIXME-CI: v_ceil_f64_e32
-; define void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
-; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
-; store <3 x double> %y, <3 x double> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}fceil_v4f64:
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-define void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
- %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
- store <4 x double> %y, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v8f64:
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-define void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
- %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
- store <8 x double> %y, <8 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fceil_v16f64:
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-; CI: v_ceil_f64_e32
-define void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
- %y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
- store <16 x double> %y, <16 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fcmp-cnd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcmp-cnd.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcmp-cnd.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcmp-cnd.ll (removed)
@@ -1,14 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;Not checking arguments 2 and 3 to CNDE, because they may change between
-;registers and literal.x depending on what the optimizer does.
-;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
-entry:
- %0 = load float, float addrspace(1)* %in
- %cmp = fcmp oeq float %0, 0.000000e+00
- %value = select i1 %cmp, i32 2, i32 3
- store i32 %value, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fcmp-cnde-int-args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcmp-cnde-int-args.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcmp-cnde-int-args.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcmp-cnde-int-args.ll (removed)
@@ -1,16 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; This test checks a bug in R600TargetLowering::LowerSELECT_CC where the
-; chance to optimize the fcmp + select instructions to SET* was missed
-; due to the fact that the operands to fcmp and select had different types
-
-; CHECK: SET{{[A-Z]+}}_DX10
-
-define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
-entry:
- %0 = load float, float addrspace(1)* %in
- %cmp = fcmp oeq float %0, 0.000000e+00
- %value = select i1 %cmp, i32 -1, i32 0
- store i32 %value, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcmp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcmp.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}fcmp_sext:
-; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
-entry:
- %0 = load float, float addrspace(1)* %in
- %arrayidx1 = getelementptr inbounds float, float addrspace(1)* %in, i32 1
- %1 = load float, float addrspace(1)* %arrayidx1
- %cmp = fcmp oeq float %0, %1
- %sext = sext i1 %cmp to i32
- store i32 %sext, i32 addrspace(1)* %out
- ret void
-}
-
-; This test checks that a setcc node with f32 operands is lowered to a
-; SET*_DX10 instruction. Previously we were lowering this to:
-; SET* + FP_TO_SINT
-
-; CHECK: {{^}}fcmp_br:
-; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
-; CHECK-NEXT {{[0-9]+(5.0}}
-
-define void @fcmp_br(i32 addrspace(1)* %out, float %in) {
-entry:
- %0 = fcmp oeq float %in, 5.0
- br i1 %0, label %IF, label %ENDIF
-
-IF:
- %1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
- store i32 0, i32 addrspace(1)* %1
- br label %ENDIF
-
-ENDIF:
- store i32 0, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fcmp64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcmp64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcmp64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcmp64.ll (removed)
@@ -1,74 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; CHECK-LABEL: {{^}}flt_f64:
-; CHECK: v_cmp_nge_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @flt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp ult double %r0, %r1
- %r3 = zext i1 %r2 to i32
- store i32 %r3, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fle_f64:
-; CHECK: v_cmp_ngt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @fle_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp ule double %r0, %r1
- %r3 = zext i1 %r2 to i32
- store i32 %r3, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fgt_f64:
-; CHECK: v_cmp_nle_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @fgt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp ugt double %r0, %r1
- %r3 = zext i1 %r2 to i32
- store i32 %r3, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fge_f64:
-; CHECK: v_cmp_nlt_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @fge_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp uge double %r0, %r1
- %r3 = zext i1 %r2 to i32
- store i32 %r3, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fne_f64:
-; CHECK: v_cmp_neq_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp une double %r0, %r1
- %r3 = select i1 %r2, double %r0, double %r1
- store double %r3, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}feq_f64:
-; CHECK: v_cmp_nlg_f64_e32 vcc, {{v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
-define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fcmp ueq double %r0, %r1
- %r3 = select i1 %r2, double %r0, double %r1
- store double %r3, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fconst64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fconst64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fconst64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fconst64.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; CHECK: {{^}}fconst_f64:
-; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0x40140000
-; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0
-
-define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
- %r1 = load double, double addrspace(1)* %in
- %r2 = fadd double %r1, 5.000000e+00
- store double %r2, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fcopysign.f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcopysign.f32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcopysign.f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcopysign.f32.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-
-declare float @llvm.copysign.f32(float, float) nounwind readnone
-declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind readnone
-
-; Try to identify arg based on higher address.
-; FUNC-LABEL: {{^}}test_copysign_f32:
-; SI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0xb
-; SI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0xc
-; VI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0x2c
-; VI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0x30
-; GCN-DAG: v_mov_b32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]]
-; GCN-DAG: v_mov_b32_e32 [[VMAG:v[0-9]+]], [[SMAG]]
-; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
-; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-
-; EG: BFI_INT
-define void @test_copysign_f32(float addrspace(1)* %out, float %mag, float %sign) nounwind {
- %result = call float @llvm.copysign.f32(float %mag, float %sign)
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copysign_v2f32:
-; GCN: s_endpgm
-
-; EG: BFI_INT
-; EG: BFI_INT
-define void @test_copysign_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %mag, <2 x float> %sign) nounwind {
- %result = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> %sign)
- store <2 x float> %result, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copysign_v4f32:
-; GCN: s_endpgm
-
-; EG: BFI_INT
-; EG: BFI_INT
-; EG: BFI_INT
-; EG: BFI_INT
-define void @test_copysign_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %mag, <4 x float> %sign) nounwind {
- %result = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag, <4 x float> %sign)
- store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/fcopysign.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fcopysign.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fcopysign.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fcopysign.f64.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-
-declare double @llvm.copysign.f64(double, double) nounwind readnone
-declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) nounwind readnone
-declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone
-
-; FUNC-LABEL: {{^}}test_copysign_f64:
-; SI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; VI-DAG: s_load_dwordx2 s{{\[}}[[SMAG_LO:[0-9]+]]:[[SMAG_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; VI-DAG: s_load_dwordx2 s{{\[}}[[SSIGN_LO:[0-9]+]]:[[SSIGN_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
-; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]]
-; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]]
-; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff
-; GCN: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]]
-; GCN: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]]
-; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}}
-; GCN: s_endpgm
-define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %sign) nounwind {
- %result = call double @llvm.copysign.f64(double %mag, double %sign)
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copysign_v2f64:
-; GCN: s_endpgm
-define void @test_copysign_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %mag, <2 x double> %sign) nounwind {
- %result = call <2 x double> @llvm.copysign.v2f64(<2 x double> %mag, <2 x double> %sign)
- store <2 x double> %result, <2 x double> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_copysign_v4f64:
-; GCN: s_endpgm
-define void @test_copysign_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %mag, <4 x double> %sign) nounwind {
- %result = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign)
- store <4 x double> %result, <4 x double> addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fdiv.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fdiv.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fdiv.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fdiv.f64.ll (removed)
@@ -1,96 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=COMMON %s
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=COMMON %s
-
-
-; COMMON-LABEL: {{^}}fdiv_f64:
-; COMMON-DAG: buffer_load_dwordx2 [[NUM:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0
-; COMMON-DAG: buffer_load_dwordx2 [[DEN:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0 offset:8
-; CI-DAG: v_div_scale_f64 [[SCALE0:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, [[DEN]], [[DEN]], [[NUM]]
-; CI-DAG: v_div_scale_f64 [[SCALE1:v\[[0-9]+:[0-9]+\]]], vcc, [[NUM]], [[DEN]], [[NUM]]
-
-; Check for div_scale bug workaround on SI
-; SI-DAG: v_div_scale_f64 [[SCALE0:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, [[DEN]], [[DEN]], [[NUM]]
-; SI-DAG: v_div_scale_f64 [[SCALE1:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, [[NUM]], [[DEN]], [[NUM]]
-
-; COMMON-DAG: v_rcp_f64_e32 [[RCP_SCALE0:v\[[0-9]+:[0-9]+\]]], [[SCALE0]]
-
-; SI-DAG: v_cmp_eq_i32_e32 vcc, {{v[0-9]+}}, {{v[0-9]+}}
-; SI-DAG: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}
-; SI-DAG: s_xor_b64 vcc, [[CMP0]], vcc
-
-; COMMON-DAG: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[RCP_SCALE0]], 1.0
-; COMMON-DAG: v_fma_f64 [[FMA1:v\[[0-9]+:[0-9]+\]]], [[RCP_SCALE0]], [[FMA0]], [[RCP_SCALE0]]
-; COMMON-DAG: v_fma_f64 [[FMA2:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[FMA1]], 1.0
-; COMMON-DAG: v_fma_f64 [[FMA3:v\[[0-9]+:[0-9]+\]]], [[FMA1]], [[FMA2]], [[FMA1]]
-; COMMON-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[SCALE1]], [[FMA3]]
-; COMMON-DAG: v_fma_f64 [[FMA4:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[MUL]], [[SCALE1]]
-; COMMON: v_div_fmas_f64 [[FMAS:v\[[0-9]+:[0-9]+\]]], [[FMA4]], [[FMA3]], [[MUL]]
-; COMMON: v_div_fixup_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[FMAS]], [[DEN]], [[NUM]]
-; COMMON: buffer_store_dwordx2 [[RESULT]]
-; COMMON: s_endpgm
-define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in) nounwind {
- %gep.1 = getelementptr double, double addrspace(1)* %in, i32 1
- %num = load double, double addrspace(1)* %in
- %den = load double, double addrspace(1)* %gep.1
- %result = fdiv double %num, %den
- store double %result, double addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}fdiv_f64_s_v:
-define void @fdiv_f64_s_v(double addrspace(1)* %out, double addrspace(1)* %in, double %num) nounwind {
- %den = load double, double addrspace(1)* %in
- %result = fdiv double %num, %den
- store double %result, double addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}fdiv_f64_v_s:
-define void @fdiv_f64_v_s(double addrspace(1)* %out, double addrspace(1)* %in, double %den) nounwind {
- %num = load double, double addrspace(1)* %in
- %result = fdiv double %num, %den
- store double %result, double addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}fdiv_f64_s_s:
-define void @fdiv_f64_s_s(double addrspace(1)* %out, double %num, double %den) nounwind {
- %result = fdiv double %num, %den
- store double %result, double addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}v_fdiv_v2f64:
-define void @v_fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in) nounwind {
- %gep.1 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in, i32 1
- %num = load <2 x double>, <2 x double> addrspace(1)* %in
- %den = load <2 x double>, <2 x double> addrspace(1)* %gep.1
- %result = fdiv <2 x double> %num, %den
- store <2 x double> %result, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}s_fdiv_v2f64:
-define void @s_fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %num, <2 x double> %den) {
- %result = fdiv <2 x double> %num, %den
- store <2 x double> %result, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}v_fdiv_v4f64:
-define void @v_fdiv_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) nounwind {
- %gep.1 = getelementptr <4 x double>, <4 x double> addrspace(1)* %in, i32 1
- %num = load <4 x double>, <4 x double> addrspace(1)* %in
- %den = load <4 x double>, <4 x double> addrspace(1)* %gep.1
- %result = fdiv <4 x double> %num, %den
- store <4 x double> %result, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; COMMON-LABEL: {{^}}s_fdiv_v4f64:
-define void @s_fdiv_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %num, <4 x double> %den) {
- %result = fdiv <4 x double> %num, %den
- store <4 x double> %result, <4 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fdiv.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fdiv.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fdiv.ll (removed)
@@ -1,68 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; These tests check that fdiv is expanded correctly and also test that the
-; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
-; instruction groups.
-
-; FUNC-LABEL: {{^}}fdiv_f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
-
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) {
-entry:
- %0 = fdiv float %a, %b
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-
-
-; FUNC-LABEL: {{^}}fdiv_v2f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
-
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
-entry:
- %0 = fdiv <2 x float> %a, %b
- store <2 x float> %0, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fdiv_v4f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-; SI-DAG: v_rcp_f32
-; SI-DAG: v_mul_f32
-define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float>, <4 x float> addrspace(1) * %in
- %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
- %result = fdiv <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fetch-limits.r600.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fetch-limits.r600.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fetch-limits.r600.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fetch-limits.r600.ll (removed)
@@ -1,48 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
-
-; R600 supports 8 fetches in a clause
-; CHECK: {{^}}fetch_limits_r600:
-; CHECK: Fetch clause
-; CHECK: Fetch clause
-
-define void @fetch_limits_r600() #0 {
-entry:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
- %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
- %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
- %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
- %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
- %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
- %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
- %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
- %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
- %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
- %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
- %a = fadd <4 x float> %res0, %res1
- %b = fadd <4 x float> %res2, %res3
- %c = fadd <4 x float> %res4, %res5
- %d = fadd <4 x float> %res6, %res7
- %e = fadd <4 x float> %res8, %a
-
- %bc = fadd <4 x float> %b, %c
- %de = fadd <4 x float> %d, %e
-
- %bcde = fadd <4 x float> %bc, %de
-
- call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1)
- ret void
-}
-
-attributes #0 = { "ShaderType"="0" } ; Pixel Shader
-
-declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Removed: llvm/trunk/test/CodeGen/R600/fetch-limits.r700+.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fetch-limits.r700%2B.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fetch-limits.r700+.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fetch-limits.r700+.ll (removed)
@@ -1,81 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=caicos | FileCheck %s
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
-
-; r700+ supports 16 fetches in a clause
-; CHECK: {{^}}fetch_limits_r700:
-; CHECK: Fetch clause
-; CHECK: Fetch clause
-
-define void @fetch_limits_r700() #0 {
-entry:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
- %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
- %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
- %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
- %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
- %9 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
- %11 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
- %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
- %13 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
- %14 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
- %15 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
- %16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
- %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
- %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
- %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
- %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
- %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
- %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
- %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
- %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
- %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
- %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 0, i32 0, i32 1)
- %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 0, i32 1)
- %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1)
- %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %12, i32 0, i32 0, i32 1)
- %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 0, i32 0, i32 1)
- %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1)
- %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 0, i32 0, i32 1)
- %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %16, i32 0, i32 0, i32 1)
- %a = fadd <4 x float> %res0, %res1
- %b = fadd <4 x float> %res2, %res3
- %c = fadd <4 x float> %res4, %res5
- %d = fadd <4 x float> %res6, %res7
- %e = fadd <4 x float> %res8, %res9
- %f = fadd <4 x float> %res10, %res11
- %g = fadd <4 x float> %res12, %res13
- %h = fadd <4 x float> %res14, %res15
- %i = fadd <4 x float> %res16, %a
-
- %bc = fadd <4 x float> %b, %c
- %de = fadd <4 x float> %d, %e
- %fg = fadd <4 x float> %f, %g
- %hi = fadd <4 x float> %h, %i
-
- %bcde = fadd <4 x float> %bc, %de
- %fghi = fadd <4 x float> %fg, %hi
-
- %bcdefghi = fadd <4 x float> %bcde, %fghi
- call void @llvm.R600.store.swizzle(<4 x float> %bcdefghi, i32 0, i32 1)
- ret void
-}
-
-attributes #0 = { "ShaderType"="0" } ; Pixel Shader
-
-declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Removed: llvm/trunk/test/CodeGen/R600/ffloor.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ffloor.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ffloor.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ffloor.f64.ll (removed)
@@ -1,127 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare double @llvm.fabs.f64(double %Val)
-declare double @llvm.floor.f64(double) nounwind readnone
-declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
-declare <3 x double> @llvm.floor.v3f64(<3 x double>) nounwind readnone
-declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
-declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone
-declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
-
-; FUNC-LABEL: {{^}}ffloor_f64:
-; CI: v_floor_f64_e32
-; SI: v_fract_f64_e32
-; SI: v_min_f64
-; SI: v_cmp_class_f64_e64
-; SI: v_cndmask_b32_e64
-; SI: v_cndmask_b32_e64
-; SI: v_add_f64
-; SI: s_endpgm
-define void @ffloor_f64(double addrspace(1)* %out, double %x) {
- %y = call double @llvm.floor.f64(double %x) nounwind readnone
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ffloor_f64_neg:
-; CI: v_floor_f64_e64
-; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT:s[[0-9]+:[0-9]+]]]
-; SI: v_min_f64
-; SI: v_cmp_class_f64_e64
-; SI: v_cndmask_b32_e64
-; SI: v_cndmask_b32_e64
-; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT]]
-; SI: s_endpgm
-define void @ffloor_f64_neg(double addrspace(1)* %out, double %x) {
- %neg = fsub double 0.0, %x
- %y = call double @llvm.floor.f64(double %neg) nounwind readnone
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ffloor_f64_neg_abs:
-; CI: v_floor_f64_e64
-; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT:s[[0-9]+:[0-9]+]]]|
-; SI: v_min_f64
-; SI: v_cmp_class_f64_e64
-; SI: v_cndmask_b32_e64
-; SI: v_cndmask_b32_e64
-; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT]]|
-; SI: s_endpgm
-define void @ffloor_f64_neg_abs(double addrspace(1)* %out, double %x) {
- %abs = call double @llvm.fabs.f64(double %x)
- %neg = fsub double 0.0, %abs
- %y = call double @llvm.floor.f64(double %neg) nounwind readnone
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ffloor_v2f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
- %y = call <2 x double> @llvm.floor.v2f64(<2 x double> %x) nounwind readnone
- store <2 x double> %y, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64:
-; FIXME-CI: v_floor_f64_e32
-; FIXME-CI: v_floor_f64_e32
-; FIXME-CI: v_floor_f64_e32
-; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
-; %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone
-; store <3 x double> %y, <3 x double> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}ffloor_v4f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
- %y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
- store <4 x double> %y, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ffloor_v8f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
- %y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone
- store <8 x double> %y, <8 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ffloor_v16f64:
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-; CI: v_floor_f64_e32
-define void @ffloor_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
- %y = call <16 x double> @llvm.floor.v16f64(<16 x double> %x) nounwind readnone
- store <16 x double> %y, <16 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ffloor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ffloor.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ffloor.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ffloor.ll (removed)
@@ -1,49 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}floor_f32:
-; SI: v_floor_f32_e32
-; R600: FLOOR
-define void @floor_f32(float addrspace(1)* %out, float %in) {
- %tmp = call float @llvm.floor.f32(float %in) #0
- store float %tmp, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}floor_v2f32:
-; SI: v_floor_f32_e32
-; SI: v_floor_f32_e32
-
-define void @floor_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
- %tmp = call <2 x float> @llvm.floor.v2f32(<2 x float> %in) #0
- store <2 x float> %tmp, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}floor_v4f32:
-; SI: v_floor_f32_e32
-; SI: v_floor_f32_e32
-; SI: v_floor_f32_e32
-; SI: v_floor_f32_e32
-
-; R600: FLOOR
-; R600: FLOOR
-; R600: FLOOR
-; R600: FLOOR
-define void @floor_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
- %tmp = call <4 x float> @llvm.floor.v4f32(<4 x float> %in) #0
- store <4 x float> %tmp, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; Function Attrs: nounwind readonly
-declare float @llvm.floor.f32(float) #0
-
-; Function Attrs: nounwind readonly
-declare <2 x float> @llvm.floor.v2f32(<2 x float>) #0
-
-; Function Attrs: nounwind readonly
-declare <4 x float> @llvm.floor.v4f32(<4 x float>) #0
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/flat-address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/flat-address-space.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/flat-address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/flat-address-space.ll (removed)
@@ -1,184 +0,0 @@
-; RUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
-; RUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
-; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
-; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
-
-; Disable optimizations in case there are optimizations added that
-; specialize away generic pointer accesses.
-
-
-; CHECK-LABEL: {{^}}branch_use_flat_i32:
-; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
-; CHECK: s_endpgm
-define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
-entry:
- %cmp = icmp ne i32 %c, 0
- br i1 %cmp, label %local, label %global
-
-local:
- %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)*
- br label %end
-
-global:
- %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
- br label %end
-
-end:
- %fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ]
- store i32 %x, i32 addrspace(4)* %fptr, align 4
-; %val = load i32, i32 addrspace(4)* %fptr, align 4
-; store i32 %val, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-
-
-; These testcases might become useless when there are optimizations to
-; remove generic pointers.
-
-; CHECK-LABEL: {{^}}store_flat_i32:
-; CHECK: v_mov_b32_e32 v[[DATA:[0-9]+]], {{s[0-9]+}}
-; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], {{s[0-9]+}}
-; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], {{s[0-9]+}}
-; CHECK: flat_store_dword v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
- %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
- store i32 %x, i32 addrspace(4)* %fptr, align 4
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_flat_i64:
-; CHECK: flat_store_dwordx2
-define void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
- %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
- store i64 %x, i64 addrspace(4)* %fptr, align 8
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_flat_v4i32:
-; CHECK: flat_store_dwordx4
-define void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
- %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
- store <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_flat_trunc_i16:
-; CHECK: flat_store_short
-define void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
- %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
- %y = trunc i32 %x to i16
- store i16 %y, i16 addrspace(4)* %fptr, align 2
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_flat_trunc_i8:
-; CHECK: flat_store_byte
-define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
- %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
- %y = trunc i32 %x to i8
- store i8 %y, i8 addrspace(4)* %fptr, align 2
- ret void
-}
-
-
-
-; CHECK-LABEL @load_flat_i32:
-; CHECK: flat_load_dword
-define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
- %fload = load i32, i32 addrspace(4)* %fptr, align 4
- store i32 %fload, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; CHECK-LABEL @load_flat_i64:
-; CHECK: flat_load_dwordx2
-define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
- %fload = load i64, i64 addrspace(4)* %fptr, align 4
- store i64 %fload, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; CHECK-LABEL @load_flat_v4i32:
-; CHECK: flat_load_dwordx4
-define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
- %fload = load <4 x i32>, <4 x i32> addrspace(4)* %fptr, align 4
- store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; CHECK-LABEL @sextload_flat_i8:
-; CHECK: flat_load_sbyte
-define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
- %fload = load i8, i8 addrspace(4)* %fptr, align 4
- %ext = sext i8 %fload to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; CHECK-LABEL @zextload_flat_i8:
-; CHECK: flat_load_ubyte
-define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
- %fload = load i8, i8 addrspace(4)* %fptr, align 4
- %ext = zext i8 %fload to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; CHECK-LABEL @sextload_flat_i16:
-; CHECK: flat_load_sshort
-define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
- %fload = load i16, i16 addrspace(4)* %fptr, align 4
- %ext = sext i16 %fload to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; CHECK-LABEL @zextload_flat_i16:
-; CHECK: flat_load_ushort
-define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
- %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
- %fload = load i16, i16 addrspace(4)* %fptr, align 4
- %ext = zext i16 %fload to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-
-
-; TODO: This should not be zero when registers are used for small
-; scratch allocations again.
-
-; Check for prologue initializing special SGPRs pointing to scratch.
-; CHECK-LABEL: {{^}}store_flat_scratch:
-; CHECK: s_movk_i32 flat_scratch_lo, 0
-; CHECK-NO-PROMOTE: s_movk_i32 flat_scratch_hi, 0x28{{$}}
-; CHECK-PROMOTE: s_movk_i32 flat_scratch_hi, 0x0{{$}}
-; CHECK: flat_store_dword
-; CHECK: s_barrier
-; CHECK: flat_load_dword
-define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
- %alloca = alloca i32, i32 9, align 4
- %x = call i32 @llvm.r600.read.tidig.x() #3
- %pptr = getelementptr i32, i32* %alloca, i32 %x
- %fptr = addrspacecast i32* %pptr to i32 addrspace(4)*
- store i32 %x, i32 addrspace(4)* %fptr
- ; Dummy call
- call void @llvm.AMDGPU.barrier.local() #1
- %reload = load i32, i32 addrspace(4)* %fptr, align 4
- store i32 %reload, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-declare void @llvm.AMDGPU.barrier.local() #1
-declare i32 @llvm.r600.read.tidig.x() #3
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind noduplicate }
-attributes #3 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/floor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/floor.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/floor.ll (original)
+++ llvm/trunk/test/CodeGen/R600/floor.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s
-
-; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = call float @floor(float %r0)
- %vec = insertelement <4 x float> undef, float %r1, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare float @floor(float) readonly
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
Removed: llvm/trunk/test/CodeGen/R600/fma-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fma-combine.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fma-combine.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fma-combine.ll (removed)
@@ -1,368 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-FASTFMAF -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-SLOWFMAF -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() #0
-declare double @llvm.fabs.f64(double) #0
-declare double @llvm.fma.f64(double, double, double) #0
-declare float @llvm.fma.f32(float, float, float) #0
-
-; (fadd (fmul x, y), z) -> (fma x, y, z)
-; FUNC-LABEL: {{^}}combine_to_fma_f64_0:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
-
- %mul = fmul double %a, %b
- %fma = fadd double %mul, %c
- store double %fma, double addrspace(1)* %gep.out
- ret void
-}
-
-; (fadd (fmul x, y), z) -> (fma x, y, z)
-; FUNC-LABEL: {{^}}combine_to_fma_f64_0_2use:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
-; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
-; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[D]]
-; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI: s_endpgm
-define void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
- %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
- %d = load double, double addrspace(1)* %gep.3
-
- %mul = fmul double %a, %b
- %fma0 = fadd double %mul, %c
- %fma1 = fadd double %mul, %d
- store double %fma0, double addrspace(1)* %gep.out.0
- store double %fma1, double addrspace(1)* %gep.out.1
- ret void
-}
-
-; (fadd x, (fmul y, z)) -> (fma y, z, x)
-; FUNC-LABEL: {{^}}combine_to_fma_f64_1:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
-
- %mul = fmul double %a, %b
- %fma = fadd double %c, %mul
- store double %fma, double addrspace(1)* %gep.out
- ret void
-}
-
-; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_0_f64:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
-
- %mul = fmul double %a, %b
- %fma = fsub double %mul, %c
- store double %fma, double addrspace(1)* %gep.out
- ret void
-}
-
-; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_f64_0_2use:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
-; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
-; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
-; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI: s_endpgm
-define void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
- %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
- %d = load double, double addrspace(1)* %gep.3
-
- %mul = fmul double %a, %b
- %fma0 = fsub double %mul, %c
- %fma1 = fsub double %mul, %d
- store double %fma0, double addrspace(1)* %gep.out.0
- store double %fma1, double addrspace(1)* %gep.out.1
- ret void
-}
-
-; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
-
- %mul = fmul double %a, %b
- %fma = fsub double %c, %mul
- store double %fma, double addrspace(1)* %gep.out
- ret void
-}
-
-; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64_2use:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
-; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
-; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[D]]
-; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI: s_endpgm
-define void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
- %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
- %d = load double, double addrspace(1)* %gep.3
-
- %mul = fmul double %a, %b
- %fma0 = fsub double %c, %mul
- %fma1 = fsub double %d, %mul
- store double %fma0, double addrspace(1)* %gep.out.0
- store double %fma1, double addrspace(1)* %gep.out.1
- ret void
-}
-
-; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
-
- %mul = fmul double %a, %b
- %mul.neg = fsub double -0.0, %mul
- %fma = fsub double %mul.neg, %c
-
- store double %fma, double addrspace(1)* %gep.out
- ret void
-}
-
-; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_neg:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
-; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[D]]
-; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI: s_endpgm
-define void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
- %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
- %d = load double, double addrspace(1)* %gep.3
-
- %mul = fmul double %a, %b
- %mul.neg = fsub double -0.0, %mul
- %fma0 = fsub double %mul.neg, %c
- %fma1 = fsub double %mul.neg, %d
-
- store double %fma0, double addrspace(1)* %gep.out.0
- store double %fma1, double addrspace(1)* %gep.out.1
- ret void
-}
-
-; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
-; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_mul:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
-; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
-; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI: s_endpgm
-define void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
- %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0
- %b = load double, double addrspace(1)* %gep.1
- %c = load double, double addrspace(1)* %gep.2
- %d = load double, double addrspace(1)* %gep.3
-
- %mul = fmul double %a, %b
- %mul.neg = fsub double -0.0, %mul
- %fma0 = fsub double %mul.neg, %c
- %fma1 = fsub double %mul, %d
-
- store double %fma0, double addrspace(1)* %gep.out.0
- store double %fma1, double addrspace(1)* %gep.out.1
- ret void
-}
-
-; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
-
-; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_0_f64:
-; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
-; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}}
-; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]], -[[Z]]
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %x = load double, double addrspace(1)* %gep.0
- %y = load double, double addrspace(1)* %gep.1
- %z = load double, double addrspace(1)* %gep.2
- %u = load double, double addrspace(1)* %gep.3
- %v = load double, double addrspace(1)* %gep.4
-
- %tmp0 = fmul double %u, %v
- %tmp1 = call double @llvm.fma.f64(double %x, double %y, double %tmp0) #0
- %tmp2 = fsub double %tmp1, %z
-
- store double %tmp2, double addrspace(1)* %gep.out
- ret void
-}
-
-; fold (fsub x, (fma y, z, (fmul u, v)))
-; -> (fma (fneg y), z, (fma (fneg u), v, x))
-
-; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_1_f64:
-; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
-; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}}
-; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}}
-; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[U]], [[V]], [[X]]
-; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @aggressive_combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
- %tid = tail call i32 @llvm.r600.read.tidig.x() #0
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
- %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
- %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
- %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
- %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
-
- %x = load double, double addrspace(1)* %gep.0
- %y = load double, double addrspace(1)* %gep.1
- %z = load double, double addrspace(1)* %gep.2
- %u = load double, double addrspace(1)* %gep.3
- %v = load double, double addrspace(1)* %gep.4
-
- %tmp0 = fmul double %u, %v
- %tmp1 = call double @llvm.fma.f64(double %y, double %z, double %tmp0) #0
- %tmp2 = fsub double %x, %tmp1
-
- store double %tmp2, double addrspace(1)* %gep.out
- ret void
-}
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/fma.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fma.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fma.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fma.f64.ll (removed)
@@ -1,47 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare double @llvm.fma.f64(double, double, double) nounwind readnone
-declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
-declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
-
-
-; FUNC-LABEL: {{^}}fma_f64:
-; SI: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2, double addrspace(1)* %in3) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = load double, double addrspace(1)* %in3
- %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %r2)
- store double %r3, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fma_v2f64:
-; SI: v_fma_f64
-; SI: v_fma_f64
-define void @fma_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
- <2 x double> addrspace(1)* %in2, <2 x double> addrspace(1)* %in3) {
- %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
- %r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
- %r2 = load <2 x double>, <2 x double> addrspace(1)* %in3
- %r3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %r0, <2 x double> %r1, <2 x double> %r2)
- store <2 x double> %r3, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fma_v4f64:
-; SI: v_fma_f64
-; SI: v_fma_f64
-; SI: v_fma_f64
-; SI: v_fma_f64
-define void @fma_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
- <4 x double> addrspace(1)* %in2, <4 x double> addrspace(1)* %in3) {
- %r0 = load <4 x double>, <4 x double> addrspace(1)* %in1
- %r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
- %r2 = load <4 x double>, <4 x double> addrspace(1)* %in3
- %r3 = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %r0, <4 x double> %r1, <4 x double> %r2)
- store <4 x double> %r3, <4 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fma.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fma.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fma.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fma.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.fma.f32(float, float, float) nounwind readnone
-declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-
-; FUNC-LABEL: {{^}}fma_f32:
-; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
-
-; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},
-; EG: FMA {{\*? *}}[[RES]]
-define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
- float addrspace(1)* %in2, float addrspace(1)* %in3) {
- %r0 = load float, float addrspace(1)* %in1
- %r1 = load float, float addrspace(1)* %in2
- %r2 = load float, float addrspace(1)* %in3
- %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
- store float %r3, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fma_v2f32:
-; SI: v_fma_f32
-; SI: v_fma_f32
-
-; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},
-; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
-; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
-define void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
- <2 x float> addrspace(1)* %in2, <2 x float> addrspace(1)* %in3) {
- %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1
- %r1 = load <2 x float>, <2 x float> addrspace(1)* %in2
- %r2 = load <2 x float>, <2 x float> addrspace(1)* %in3
- %r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)
- store <2 x float> %r3, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fma_v4f32:
-; SI: v_fma_f32
-; SI: v_fma_f32
-; SI: v_fma_f32
-; SI: v_fma_f32
-
-; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},
-; EG-DAG: FMA {{\*? *}}[[RES]].X
-; EG-DAG: FMA {{\*? *}}[[RES]].Y
-; EG-DAG: FMA {{\*? *}}[[RES]].Z
-; EG-DAG: FMA {{\*? *}}[[RES]].W
-define void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
- <4 x float> addrspace(1)* %in2, <4 x float> addrspace(1)* %in3) {
- %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1
- %r1 = load <4 x float>, <4 x float> addrspace(1)* %in2
- %r2 = load <4 x float>, <4 x float> addrspace(1)* %in3
- %r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)
- store <4 x float> %r3, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @fma_commute_mul_inline_imm_f32
-; SI: v_fma_f32 {{v[0-9]+}}, 2.0, {{v[0-9]+}}, {{v[0-9]+}}
-define void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
- %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
- %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
- %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %a = load float, float addrspace(1)* %in.a.gep, align 4
- %b = load float, float addrspace(1)* %in.b.gep, align 4
-
- %fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)
- store float %fma, float addrspace(1)* %out.gep, align 4
- ret void
-}
-
-; FUNC-LABEL: @fma_commute_mul_s_f32
-define void @fma_commute_mul_s_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b, float %b) nounwind {
- %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
- %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
- %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %a = load float, float addrspace(1)* %in.a.gep, align 4
- %c = load float, float addrspace(1)* %in.b.gep, align 4
-
- %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
- store float %fma, float addrspace(1)* %out.gep, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fmad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmad.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmad.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmad.ll (removed)
@@ -1,19 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = extractelement <4 x float> %reg0, i32 1
- %r2 = extractelement <4 x float> %reg0, i32 2
- %r3 = fmul float %r0, %r1
- %r4 = fadd float %r3, %r2
- %vec = insertelement <4 x float> undef, float %r4, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare float @fabs(float ) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/fmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax.ll (removed)
@@ -1,17 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = extractelement <4 x float> %reg0, i32 1
- %r2 = fcmp oge float %r0, %r1
- %r3 = select i1 %r2, float %r0, float %r1
- %vec = insertelement <4 x float> undef, float %r3, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/fmax3.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax3.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax3.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax3.f64.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare double @llvm.maxnum.f64(double, double) nounwind readnone
-
-; SI-LABEL: {{^}}test_fmax3_f64:
-; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0{{$}}
-; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:8
-; SI-DAG: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:16
-; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]]
-; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGC]]
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
-define void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
- %bptr = getelementptr double, double addrspace(1)* %aptr, i32 1
- %cptr = getelementptr double, double addrspace(1)* %aptr, i32 2
- %a = load double, double addrspace(1)* %aptr, align 8
- %b = load double, double addrspace(1)* %bptr, align 8
- %c = load double, double addrspace(1)* %cptr, align 8
- %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
- %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
- store double %f1, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fmax3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax3.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax3.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax3.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.maxnum.f32(float, float) nounwind readnone
-
-; SI-LABEL: {{^}}test_fmax3_olt_0:
-; SI: buffer_load_dword [[REGC:v[0-9]+]]
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
- %a = load float, float addrspace(1)* %aptr, align 4
- %b = load float, float addrspace(1)* %bptr, align 4
- %c = load float, float addrspace(1)* %cptr, align 4
- %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
- %f1 = call float @llvm.maxnum.f32(float %f0, float %c) nounwind readnone
- store float %f1, float addrspace(1)* %out, align 4
- ret void
-}
-
-; Commute operand of second fmax
-; SI-LABEL: {{^}}test_fmax3_olt_1:
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: buffer_load_dword [[REGC:v[0-9]+]]
-; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_fmax3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
- %a = load float, float addrspace(1)* %aptr, align 4
- %b = load float, float addrspace(1)* %bptr, align 4
- %c = load float, float addrspace(1)* %cptr, align 4
- %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
- %f1 = call float @llvm.maxnum.f32(float %c, float %f0) nounwind readnone
- store float %f1, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fmax_legacy.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax_legacy.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax_legacy.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax_legacy.f64.ll (removed)
@@ -1,67 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; Make sure we don't try to form FMAX_LEGACY nodes with f64
-
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; FUNC-LABEL: @test_fmax_legacy_uge_f64
-define void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp uge double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_oge_f64
-define void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp oge double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_ugt_f64
-define void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp ugt double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_ogt_f64
-define void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp ogt double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmax_legacy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax_legacy.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax_legacy.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax_legacy.ll (removed)
@@ -1,116 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FIXME: Should replace unsafe-fp-math with no signed zeros.
-
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; FUNC-LABEL: @test_fmax_legacy_uge_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-
-; EG: MAX
-define void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp uge float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_oge_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; EG: MAX
-define void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp oge float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_ugt_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; EG: MAX
-define void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ugt float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_legacy_ogt_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; EG: MAX
-define void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ogt float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-
-; FUNC-LABEL: @test_fmax_legacy_ogt_f32_multi_use
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-NOT: v_max_
-; SI: v_cmp_gt_f32
-; SI-NEXT: v_cndmask_b32
-; SI-NOT: v_max_
-
-; EG: MAX
-define void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ogt float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out0, align 4
- store i1 %cmp, i1addrspace(1)* %out1
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmaxnum.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmaxnum.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmaxnum.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmaxnum.f64.ll (removed)
@@ -1,76 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare double @llvm.maxnum.f64(double, double) #0
-declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) #0
-declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>) #0
-declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>) #0
-declare <16 x double> @llvm.maxnum.v16f64(<16 x double>, <16 x double>) #0
-
-; FUNC-LABEL: @test_fmax_f64
-; SI: v_max_f64
-define void @test_fmax_f64(double addrspace(1)* %out, double %a, double %b) nounwind {
- %val = call double @llvm.maxnum.f64(double %a, double %b) #0
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v2f64
-; SI: v_max_f64
-; SI: v_max_f64
-define void @test_fmax_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
- %val = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b) #0
- store <2 x double> %val, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v4f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-define void @test_fmax_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
- %val = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %a, <4 x double> %b) #0
- store <4 x double> %val, <4 x double> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v8f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-define void @test_fmax_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
- %val = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %a, <8 x double> %b) #0
- store <8 x double> %val, <8 x double> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v16f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-; SI: v_max_f64
-define void @test_fmax_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
- %val = call <16 x double> @llvm.maxnum.v16f64(<16 x double> %a, <16 x double> %b) #0
- store <16 x double> %val, <16 x double> addrspace(1)* %out, align 128
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmaxnum.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmaxnum.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmaxnum.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmaxnum.ll (removed)
@@ -1,283 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare float @llvm.maxnum.f32(float, float) #0
-declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0
-declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #0
-declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #0
-declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #0
-
-declare double @llvm.maxnum.f64(double, double)
-
-; FUNC-LABEL: @test_fmax_f32
-; SI: v_max_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
- %val = call float @llvm.maxnum.f32(float %a, float %b) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v2f32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
- %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) #0
- store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v4f32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-; EG: MAX_DX10 {{.*}}[[OUT]]
-define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
- %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) #0
- store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v8f32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
-define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
- %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) #0
- store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: @test_fmax_v16f32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-; SI: v_max_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
-; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].W
-; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].X
-; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Y
-; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Z
-; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].W
-define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
- %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0
- store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_nan_nan
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-; EG: 2143289344(nan)
-define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_val_nan
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_nan_val
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_p0_p0
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_p0_n0
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_n0_p0
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmax_f32_n0_n0
-; SI-NOT: v_max_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmax_var_immediate_f32
-; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MAX_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.maxnum.f32(float %a, float 2.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmax_immediate_var_f32
-; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.maxnum.f32(float 2.0, float %a) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmax_var_literal_f32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.maxnum.f32(float %a, float 99.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmax_literal_var_f32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.maxnum.f32(float 99.0, float %a) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmin.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmin.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmin.ll (removed)
@@ -1,17 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = extractelement <4 x float> %reg0, i32 1
- %r2 = fcmp uge float %r0, %r1
- %r3 = select i1 %r2, float %r1, float %r0
- %vec = insertelement <4 x float> undef, float %r3, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/fmin3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmin3.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmin3.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmin3.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.minnum.f32(float, float) nounwind readnone
-
-; SI-LABEL: {{^}}test_fmin3_olt_0:
-; SI: buffer_load_dword [[REGC:v[0-9]+]]
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
- %a = load float, float addrspace(1)* %aptr, align 4
- %b = load float, float addrspace(1)* %bptr, align 4
- %c = load float, float addrspace(1)* %cptr, align 4
- %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
- %f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone
- store float %f1, float addrspace(1)* %out, align 4
- ret void
-}
-
-; Commute operand of second fmin
-; SI-LABEL: {{^}}test_fmin3_olt_1:
-; SI: buffer_load_dword [[REGB:v[0-9]+]]
-; SI: buffer_load_dword [[REGA:v[0-9]+]]
-; SI: buffer_load_dword [[REGC:v[0-9]+]]
-; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
- %a = load float, float addrspace(1)* %aptr, align 4
- %b = load float, float addrspace(1)* %bptr, align 4
- %c = load float, float addrspace(1)* %cptr, align 4
- %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
- %f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone
- store float %f1, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fmin_legacy.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmin_legacy.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmin_legacy.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmin_legacy.f64.ll (removed)
@@ -1,77 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; FUNC-LABEL: @test_fmin_legacy_f64
-define void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double> inreg %reg0) #0 {
- %r0 = extractelement <4 x double> %reg0, i32 0
- %r1 = extractelement <4 x double> %reg0, i32 1
- %r2 = fcmp uge double %r0, %r1
- %r3 = select i1 %r2, double %r1, double %r0
- %vec = insertelement <4 x double> undef, double %r3, i32 0
- store <4 x double> %vec, <4 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ule_f64
-define void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp ule double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ole_f64
-define void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp ole double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_olt_f64
-define void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp olt double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ult_f64
-define void @test_fmin_legacy_ult_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %cmp = fcmp ult double %a, %b
- %val = select i1 %cmp, double %a, double %b
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmin_legacy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmin_legacy.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmin_legacy.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmin_legacy.ll (removed)
@@ -1,123 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FIXME: Should replace unsafe-fp-math with no signed zeros.
-
-declare i32 @llvm.r600.read.tidig.x() #1
-
-; FUNC-LABEL: @test_fmin_legacy_f32
-; EG: MIN *
-; SI-SAFE: v_min_legacy_f32_e32
-; SI-NONAN: v_min_f32_e32
-define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = extractelement <4 x float> %reg0, i32 1
- %r2 = fcmp uge float %r0, %r1
- %r3 = select i1 %r2, float %r1, float %r0
- %vec = insertelement <4 x float> undef, float %r3, i32 0
- store <4 x float> %vec, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ule_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-define void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ule float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ole_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-define void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ole float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_olt_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
-; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-define void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp olt float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ult_f32
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
-define void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ult float %a, %b
- %val = select i1 %cmp, float %a, float %b
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_legacy_ole_f32_multi_use
-; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI-NOT: v_min
-; SI: v_cmp_le_f32
-; SI-NEXT: v_cndmask_b32
-; SI-NOT: v_min
-; SI: s_endpgm
-define void @test_fmin_legacy_ole_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %cmp = fcmp ole float %a, %b
- %val0 = select i1 %cmp, float %a, float %b
- store float %val0, float addrspace(1)* %out0, align 4
- store i1 %cmp, i1 addrspace(1)* %out1
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fminnum.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fminnum.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fminnum.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fminnum.f64.ll (removed)
@@ -1,76 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare double @llvm.minnum.f64(double, double) #0
-declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) #0
-declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>) #0
-declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>) #0
-declare <16 x double> @llvm.minnum.v16f64(<16 x double>, <16 x double>) #0
-
-; FUNC-LABEL: @test_fmin_f64
-; SI: v_min_f64
-define void @test_fmin_f64(double addrspace(1)* %out, double %a, double %b) nounwind {
- %val = call double @llvm.minnum.f64(double %a, double %b) #0
- store double %val, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v2f64
-; SI: v_min_f64
-; SI: v_min_f64
-define void @test_fmin_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
- %val = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b) #0
- store <2 x double> %val, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v4f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-define void @test_fmin_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
- %val = call <4 x double> @llvm.minnum.v4f64(<4 x double> %a, <4 x double> %b) #0
- store <4 x double> %val, <4 x double> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v8f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-define void @test_fmin_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
- %val = call <8 x double> @llvm.minnum.v8f64(<8 x double> %a, <8 x double> %b) #0
- store <8 x double> %val, <8 x double> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v16f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-; SI: v_min_f64
-define void @test_fmin_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
- %val = call <16 x double> @llvm.minnum.v16f64(<16 x double> %a, <16 x double> %b) #0
- store <16 x double> %val, <16 x double> addrspace(1)* %out, align 128
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fminnum.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fminnum.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fminnum.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fminnum.ll (removed)
@@ -1,281 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.minnum.f32(float, float) #0
-declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0
-declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #0
-declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #0
-declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0
-
-; FUNC-LABEL: @test_fmin_f32
-; SI: v_min_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
- %val = call float @llvm.minnum.f32(float %a, float %b) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v2f32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
- %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0
- store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v4f32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-; EG: MIN_DX10 {{.*}}[[OUT]]
-define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
- %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0
- store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v8f32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
-define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
- %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0
- store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
-
-; FUNC-LABEL: @test_fmin_v16f32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-; SI: v_min_f32_e32
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
-; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W
-; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X
-; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y
-; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z
-; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W
-define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
- %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0
- store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_nan_nan
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-; EG: 2143289344({{nan|1\.#QNAN0e\+00}})
-define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_val_nan
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_nan_val
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_p0_p0
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_p0_n0
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0
-; SI-NOT: v_min_f32_e32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; SI: buffer_store_dword [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG-NOT: MIN_DX10
-; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
-define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind {
- %val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmin_var_immediate_f32
-; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.minnum.f32(float %a, float 2.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmin_immediate_var_f32
-; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.minnum.f32(float 2.0, float %a) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmin_var_literal_f32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.minnum.f32(float %a, float 99.0) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @fmin_literal_var_f32
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
-; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
-; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
-define void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
- %val = call float @llvm.minnum.f32(float 99.0, float %a) #0
- store float %val, float addrspace(1)* %out, align 4
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmul.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmul.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmul.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-
-; FUNC-LABEL: {{^}}fmul_f32:
-; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
-
-; SI: v_mul_f32
-define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) {
-entry:
- %0 = fmul float %a, %b
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
-
-; FUNC-LABEL: {{^}}fmul_v2f32:
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
-
-; SI: v_mul_f32
-; SI: v_mul_f32
-define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
-entry:
- %0 = fmul <2 x float> %a, %b
- store <2 x float> %0, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fmul_v4f32:
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_mul_f32
-; SI: v_mul_f32
-; SI: v_mul_f32
-; SI: v_mul_f32
-define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float>, <4 x float> addrspace(1) * %in
- %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
- %result = fmul <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_mul_2_k:
-; SI: v_mul_f32
-; SI-NOT: v_mul_f32
-; SI: s_endpgm
-define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 {
- %y = fmul float %x, 2.0
- %z = fmul float %y, 3.0
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}test_mul_2_k_inv:
-; SI: v_mul_f32
-; SI-NOT: v_mul_f32
-; SI-NOT: v_mad_f32
-; SI: s_endpgm
-define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 {
- %y = fmul float %x, 3.0
- %z = fmul float %y, 2.0
- store float %z, float addrspace(1)* %out
- ret void
-}
-
-; There should be three multiplies here; %a should be used twice (once
-; negated), not duplicated into mul x, 5.0 and mul x, -5.0.
-; FUNC-LABEL: {{^}}test_mul_twouse:
-; SI: v_mul_f32
-; SI: v_mul_f32
-; SI: v_mul_f32
-; SI-NOT: v_mul_f32
-define void @test_mul_twouse(float addrspace(1)* %out, float %x, float %y) #0 {
- %a = fmul float %x, 5.0
- %b = fsub float -0.0, %a
- %c = fmul float %b, %y
- %d = fmul float %c, %a
- store float %d, float addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" }
Removed: llvm/trunk/test/CodeGen/R600/fmul64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmul64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmul64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmul64.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
-
-; FUNC-LABEL: {{^}}fmul_f64:
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fmul double %r0, %r1
- store double %r2, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fmul_v2f64:
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-define void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
- <2 x double> addrspace(1)* %in2) {
- %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
- %r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
- %r2 = fmul <2 x double> %r0, %r1
- store <2 x double> %r2, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fmul_v4f64:
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-define void @fmul_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
- <4 x double> addrspace(1)* %in2) {
- %r0 = load <4 x double>, <4 x double> addrspace(1)* %in1
- %r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
- %r2 = fmul <4 x double> %r0, %r1
- store <4 x double> %r2, <4 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fmuladd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmuladd.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmuladd.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmuladd.ll (removed)
@@ -1,199 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-
-declare float @llvm.fmuladd.f32(float, float, float)
-declare double @llvm.fmuladd.f64(double, double, double)
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-declare float @llvm.fabs.f32(float) nounwind readnone
-
-; CHECK-LABEL: {{^}}fmuladd_f32:
-; CHECK: v_mad_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
-
-define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
- float addrspace(1)* %in2, float addrspace(1)* %in3) {
- %r0 = load float, float addrspace(1)* %in1
- %r1 = load float, float addrspace(1)* %in2
- %r2 = load float, float addrspace(1)* %in3
- %r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
- store float %r3, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fmuladd_f64:
-; CHECK: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-
-define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2, double addrspace(1)* %in3) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = load double, double addrspace(1)* %in3
- %r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
- store double %r3, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fmuladd_2.0_a_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fmuladd_a_2.0_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fadd_a_a_b_f32:
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fadd_a_a_b_f32(float addrspace(1)* %out,
- float addrspace(1)* %in1,
- float addrspace(1)* %in2) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r0 = load float, float addrspace(1)* %gep.0
- %r1 = load float, float addrspace(1)* %gep.1
-
- %add.0 = fadd float %r0, %r0
- %add.1 = fadd float %add.0, %r1
- store float %add.1, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fadd_b_a_a_f32:
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fadd_b_a_a_f32(float addrspace(1)* %out,
- float addrspace(1)* %in1,
- float addrspace(1)* %in2) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r0 = load float, float addrspace(1)* %gep.0
- %r1 = load float, float addrspace(1)* %gep.1
-
- %add.0 = fadd float %r0, %r0
- %add.1 = fadd float %r1, %add.0
- store float %add.1, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r1.fneg = fsub float -0.000000e+00, %r1
-
- %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1.fneg, float %r2)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r1.fneg = fsub float -0.000000e+00, %r1
-
- %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1.fneg, float %r2)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32
-; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
-; CHECK: buffer_store_dword [[RESULT]]
-define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
-
- %r1 = load float, float addrspace(1)* %gep.0
- %r2 = load float, float addrspace(1)* %gep.1
-
- %r2.fneg = fsub float -0.000000e+00, %r2
-
- %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2.fneg)
- store float %r3, float addrspace(1)* %gep.out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fnearbyint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fnearbyint.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fnearbyint.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fnearbyint.ll (removed)
@@ -1,58 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s
-
-; This should have the exactly the same output as the test for rint,
-; so no need to check anything.
-
-declare float @llvm.nearbyint.f32(float) #0
-declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #0
-declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #0
-declare double @llvm.nearbyint.f64(double) #0
-declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0
-declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
-
-
-define void @fnearbyint_f32(float addrspace(1)* %out, float %in) #1 {
-entry:
- %0 = call float @llvm.nearbyint.f32(float %in)
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-define void @fnearbyint_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #1 {
-entry:
- %0 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %in)
- store <2 x float> %0, <2 x float> addrspace(1)* %out
- ret void
-}
-
-define void @fnearbyint_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #1 {
-entry:
- %0 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %in)
- store <4 x float> %0, <4 x float> addrspace(1)* %out
- ret void
-}
-
-define void @nearbyint_f64(double addrspace(1)* %out, double %in) {
-entry:
- %0 = call double @llvm.nearbyint.f64(double %in)
- store double %0, double addrspace(1)* %out
- ret void
-}
-define void @nearbyint_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
-entry:
- %0 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %in)
- store <2 x double> %0, <2 x double> addrspace(1)* %out
- ret void
-}
-
-define void @nearbyint_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
-entry:
- %0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
- store <4 x double> %0, <4 x double> addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { nounwind readonly }
-attributes #1 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg-fabs.f64.ll (removed)
@@ -1,100 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FIXME: Check something here. Currently it seems fabs + fneg aren't
-; into 2 modifiers, although theoretically that should work.
-
-; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
-define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
- %fabs = call double @llvm.fabs.f64(double %x)
- %fsub = fsub double -0.000000e+00, %fabs
- %fadd = fadd double %y, %fsub
- store double %fadd, double addrspace(1)* %out, align 8
- ret void
-}
-
-define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
- %x = load double, double addrspace(1)* %xptr, align 8
- %y = load double, double addrspace(1)* %xptr, align 8
- %fabs = call double @llvm.fabs.f64(double %x)
- %fsub = fsub double -0.000000e+00, %fabs
- %fadd = fadd double %y, %fsub
- store double %fadd, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_fmul_f64:
-; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}|
-define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
- %fabs = call double @llvm.fabs.f64(double %x)
- %fsub = fsub double -0.000000e+00, %fabs
- %fmul = fmul double %y, %fsub
- store double %fmul, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_free_f64:
-define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
- %bc = bitcast i64 %in to double
- %fabs = call double @llvm.fabs.f64(double %bc)
- %fsub = fsub double -0.000000e+00, %fabs
- store double %fsub, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
- %bc = bitcast i64 %in to double
- %fabs = call double @fabs(double %bc)
- %fsub = fsub double -0.000000e+00, %fabs
- store double %fsub, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_f64:
-; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
-; SI: s_load_dwordx2
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
-; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
-; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
-define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
- %fabs = call double @llvm.fabs.f64(double %in)
- %fsub = fsub double -0.000000e+00, %fabs
- store double %fsub, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_v2f64:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI-NOT: 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
- %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
- %fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
- store <2 x double> %fsub, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_v4f64:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI-NOT: 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
- %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
- %fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
- store <4 x double> %fsub, <4 x double> addrspace(1)* %out
- ret void
-}
-
-declare double @fabs(double) readnone
-declare double @llvm.fabs.f64(double) readnone
-declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
-declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
Removed: llvm/trunk/test/CodeGen/R600/fneg-fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg-fabs.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg-fabs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg-fabs.ll (removed)
@@ -1,118 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32:
-; SI-NOT: and
-; SI: v_sub_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
-define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
- %fabs = call float @llvm.fabs.f32(float %x)
- %fsub = fsub float -0.000000e+00, %fabs
- %fadd = fadd float %y, %fsub
- store float %fadd, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32:
-; SI-NOT: and
-; SI: v_mul_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}|
-; SI-NOT: and
-define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
- %fabs = call float @llvm.fabs.f32(float %x)
- %fsub = fsub float -0.000000e+00, %fabs
- %fmul = fmul float %y, %fsub
- store float %fmul, float addrspace(1)* %out, align 4
- ret void
-}
-
-; DAGCombiner will transform:
-; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
-; unless isFabsFree returns true
-
-; FUNC-LABEL: {{^}}fneg_fabs_free_f32:
-; R600-NOT: AND
-; R600: |PV.{{[XYZW]}}|
-; R600: -PV
-
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
- %bc = bitcast i32 %in to float
- %fabs = call float @llvm.fabs.f32(float %bc)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32:
-; R600-NOT: AND
-; R600: |PV.{{[XYZW]}}|
-; R600: -PV
-
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
- %bc = bitcast i32 %in to float
- %fabs = call float @fabs(float %bc)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_f32:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
- %fabs = call float @llvm.fabs.f32(float %in)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_fneg_fabs_f32:
-; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
-define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %val = load float, float addrspace(1)* %in, align 4
- %fabs = call float @llvm.fabs.f32(float %val)
- %fsub = fsub float -0.000000e+00, %fabs
- store float %fsub, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fabs_v2f32:
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: -PV
-; R600: |{{(PV|T[0-9])\.[XYZW]}}|
-; R600: -PV
-
-; FIXME: SGPR should be used directly for first src operand.
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI-NOT: 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
- %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
- %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
- store <2 x float> %fsub, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FIXME: SGPR should be used directly for first src operand.
-; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
-; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
-; SI-NOT: 0x80000000
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
-define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
- %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
- %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
- store <4 x float> %fsub, <4 x float> addrspace(1)* %out
- ret void
-}
-
-declare float @fabs(float) readnone
-declare float @llvm.fabs.f32(float) readnone
-declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
Removed: llvm/trunk/test/CodeGen/R600/fneg.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg.f64.ll (removed)
@@ -1,60 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}fneg_f64:
-; GCN: v_xor_b32
-define void @fneg_f64(double addrspace(1)* %out, double %in) {
- %fneg = fsub double -0.000000e+00, %in
- store double %fneg, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_v2f64:
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> %in) {
- %fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
- store <2 x double> %fneg, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_v4f64:
-; R600: -PV
-; R600: -T
-; R600: -PV
-; R600: -PV
-
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> %in) {
- %fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
- store <4 x double> %fneg, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; DAGCombiner will transform:
-; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
-; unless the target returns true for isNegFree()
-
-; FUNC-LABEL: {{^}}fneg_free_f64:
-; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, 0, -{{s\[[0-9]+:[0-9]+\]$}}
-define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
- %bc = bitcast i64 %in to double
- %fsub = fsub double 0.0, %bc
- store double %fsub, double addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}fneg_fold_f64:
-; SI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN-NOT: xor
-; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]]
-define void @fneg_fold_f64(double addrspace(1)* %out, double %in) {
- %fsub = fsub double -0.0, %in
- %fmul = fmul double %fsub, %in
- store double %fmul, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fneg.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fneg.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fneg.ll (removed)
@@ -1,70 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}fneg_f32:
-; R600: -PV
-
-; GCN: v_xor_b32
-define void @fneg_f32(float addrspace(1)* %out, float %in) {
- %fneg = fsub float -0.000000e+00, %in
- store float %fneg, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_v2f32:
-; R600: -PV
-; R600: -PV
-
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
- %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
- store <2 x float> %fneg, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_v4f32:
-; R600: -PV
-; R600: -T
-; R600: -PV
-; R600: -PV
-
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-; GCN: v_xor_b32
-define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
- %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
- store <4 x float> %fneg, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; DAGCombiner will transform:
-; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
-; unless the target returns true for isNegFree()
-
-; FUNC-LABEL: {{^}}fneg_free_f32:
-; R600-NOT: XOR
-; R600: -KC0[2].Z
-
-; XXX: We could use v_add_f32_e64 with the negate bit here instead.
-; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
-define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
- %bc = bitcast i32 %in to float
- %fsub = fsub float 0.0, %bc
- store float %fsub, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fneg_fold_f32:
-; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
-; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
-; GCN-NOT: xor
-; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
-define void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
- %fsub = fsub float -0.0, %in
- %fmul = fmul float %fsub, %in
- store float %fmul, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fp-classify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp-classify.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp-classify.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp-classify.ll (removed)
@@ -1,131 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
-declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
-declare i32 @llvm.r600.read.tidig.x() #1
-declare float @llvm.fabs.f32(float) #1
-declare double @llvm.fabs.f64(double) #1
-
-; SI-LABEL: {{^}}test_isinf_pattern:
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
-; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
-; SI-NOT: v_cmp
-; SI: s_endpgm
-define void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %fabs = tail call float @llvm.fabs.f32(float %x) #1
- %cmp = fcmp oeq float %fabs, 0x7FF0000000000000
- %ext = zext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_not_isinf_pattern_0:
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %fabs = tail call float @llvm.fabs.f32(float %x) #1
- %cmp = fcmp ueq float %fabs, 0x7FF0000000000000
- %ext = zext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_not_isinf_pattern_1:
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %fabs = tail call float @llvm.fabs.f32(float %x) #1
- %cmp = fcmp oeq float %fabs, 0xFFF0000000000000
- %ext = zext i1 %cmp to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_isfinite_pattern_0:
-; SI-NOT: v_cmp
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
-; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
-; SI-NOT: v_cmp
-; SI: s_endpgm
-define void @test_isfinite_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %ord = fcmp ord float %x, 0.000000e+00
- %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
- %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Use negative infinity
-; SI-LABEL: {{^}}test_isfinite_not_pattern_0:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
-define void @test_isfinite_not_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %ord = fcmp ord float %x, 0.000000e+00
- %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
- %ninf = fcmp une float %x.fabs, 0xFFF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; No fabs
-; SI-LABEL: {{^}}test_isfinite_not_pattern_1:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
-define void @test_isfinite_not_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %ord = fcmp ord float %x, 0.000000e+00
- %ninf = fcmp une float %x, 0x7FF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; fabs of different value
-; SI-LABEL: {{^}}test_isfinite_not_pattern_2:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
-define void @test_isfinite_not_pattern_2(i32 addrspace(1)* nocapture %out, float %x, float %y) #0 {
- %ord = fcmp ord float %x, 0.000000e+00
- %x.fabs = tail call float @llvm.fabs.f32(float %y) #1
- %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Wrong ordered compare type
-; SI-LABEL: {{^}}test_isfinite_not_pattern_3:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
-define void @test_isfinite_not_pattern_3(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %ord = fcmp uno float %x, 0.000000e+00
- %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
- %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Wrong unordered compare
-; SI-LABEL: {{^}}test_isfinite_not_pattern_4:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
-define void @test_isfinite_not_pattern_4(i32 addrspace(1)* nocapture %out, float %x) #0 {
- %ord = fcmp ord float %x, 0.000000e+00
- %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
- %ninf = fcmp one float %x.fabs, 0x7FF0000000000000
- %and = and i1 %ord, %ninf
- %ext = zext i1 %and to i32
- store i32 %ext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp16_to_fp.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
-declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
-
-; SI-LABEL: {{^}}test_convert_fp16_to_fp32:
-; SI: buffer_load_ushort [[VAL:v[0-9]+]]
-; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]]
-define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
- %val = load i16, i16 addrspace(1)* %in, align 2
- %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-
-; SI-LABEL: {{^}}test_convert_fp16_to_fp64:
-; SI: buffer_load_ushort [[VAL:v[0-9]+]]
-; SI: v_cvt_f32_f16_e32 [[RESULT32:v[0-9]+]], [[VAL]]
-; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
-; SI: buffer_store_dwordx2 [[RESULT]]
-define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
- %val = load i16, i16 addrspace(1)* %in, align 2
- %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
- store double %cvt, double addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp32_to_fp16.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
-
-; SI-LABEL: {{^}}test_convert_fp32_to_fp16:
-; SI: buffer_load_dword [[VAL:v[0-9]+]]
-; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_short [[RESULT]]
-define void @test_convert_fp32_to_fp16(i16 addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
- %val = load float, float addrspace(1)* %in, align 4
- %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
- store i16 %cvt, i16 addrspace(1)* %out, align 2
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fp_to_sint.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_sint.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_sint.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp_to_sint.f64.ll (removed)
@@ -1,56 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-
-; FUNC-LABEL: @fp_to_sint_f64_i32
-; SI: v_cvt_i32_f64_e32
-define void @fp_to_sint_f64_i32(i32 addrspace(1)* %out, double %in) {
- %result = fptosi double %in to i32
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @fp_to_sint_v2f64_v2i32
-; SI: v_cvt_i32_f64_e32
-; SI: v_cvt_i32_f64_e32
-define void @fp_to_sint_v2f64_v2i32(<2 x i32> addrspace(1)* %out, <2 x double> %in) {
- %result = fptosi <2 x double> %in to <2 x i32>
- store <2 x i32> %result, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @fp_to_sint_v4f64_v4i32
-; SI: v_cvt_i32_f64_e32
-; SI: v_cvt_i32_f64_e32
-; SI: v_cvt_i32_f64_e32
-; SI: v_cvt_i32_f64_e32
-define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> %in) {
- %result = fptosi <4 x double> %in to <4 x i32>
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: @fp_to_sint_i64_f64
-; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
-; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
-; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
-; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
-
-; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
-; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
-
-; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
-
-; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
-; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
-; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]]
-; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
-define void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
- %val = load double, double addrspace(1)* %gep, align 8
- %cast = fptosi double %val to i64
- store i64 %cast, i64 addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fp_to_sint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_sint.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_sint.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp_to_sint.ll (removed)
@@ -1,230 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
-
-declare float @llvm.fabs.f32(float) #0
-
-; FUNC-LABEL: {{^}}fp_to_sint_i32:
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; SI: v_cvt_i32_f32_e32
-; SI: s_endpgm
-define void @fp_to_sint_i32(i32 addrspace(1)* %out, float %in) {
- %conv = fptosi float %in to i32
- store i32 %conv, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_sint_i32_fabs:
-; SI: v_cvt_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
-define void @fp_to_sint_i32_fabs(i32 addrspace(1)* %out, float %in) {
- %in.fabs = call float @llvm.fabs.f32(float %in) #0
- %conv = fptosi float %in.fabs to i32
- store i32 %conv, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_sint_v2i32:
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; SI: v_cvt_i32_f32_e32
-; SI: v_cvt_i32_f32_e32
-define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
- %result = fptosi <2 x float> %in to <2 x i32>
- store <2 x i32> %result, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_sint_v4i32:
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}}
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; SI: v_cvt_i32_f32_e32
-; SI: v_cvt_i32_f32_e32
-; SI: v_cvt_i32_f32_e32
-; SI: v_cvt_i32_f32_e32
-define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %value = load <4 x float>, <4 x float> addrspace(1) * %in
- %result = fptosi <4 x float> %value to <4 x i32>
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_sint_i64:
-
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; Check that the compiler doesn't crash with a "cannot select" error
-; SI: s_endpgm
-define void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
-entry:
- %0 = fptosi float %in to i64
- store i64 %0, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC: {{^}}fp_to_sint_v2i64:
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: s_endpgm
-define void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
- %conv = fptosi <2 x float> %x to <2 x i64>
- store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC: {{^}}fp_to_sint_v4i64:
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: s_endpgm
-define void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
- %conv = fptosi <4 x float> %x to <4 x i64>
- store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/fp_to_uint.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_uint.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_uint.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp_to_uint.f64.ll (removed)
@@ -1,70 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-
-; SI-LABEL: {{^}}fp_to_uint_i32_f64:
-; SI: v_cvt_u32_f64_e32
-define void @fp_to_uint_i32_f64(i32 addrspace(1)* %out, double %in) {
- %cast = fptoui double %in to i32
- store i32 %cast, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: @fp_to_uint_v2i32_v2f64
-; SI: v_cvt_u32_f64_e32
-; SI: v_cvt_u32_f64_e32
-define void @fp_to_uint_v2i32_v2f64(<2 x i32> addrspace(1)* %out, <2 x double> %in) {
- %cast = fptoui <2 x double> %in to <2 x i32>
- store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: @fp_to_uint_v4i32_v4f64
-; SI: v_cvt_u32_f64_e32
-; SI: v_cvt_u32_f64_e32
-; SI: v_cvt_u32_f64_e32
-; SI: v_cvt_u32_f64_e32
-define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> %in) {
- %cast = fptoui <4 x double> %in to <4 x i32>
- store <4 x i32> %cast, <4 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: @fp_to_uint_i64_f64
-; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
-; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
-; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
-; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
-
-; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
-; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
-
-; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
-
-; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]]
-; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
-; CI-DAG: v_cvt_u32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]]
-; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
-define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
- %val = load double, double addrspace(1)* %gep, align 8
- %cast = fptoui double %val to i64
- store i64 %cast, i64 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: @fp_to_uint_v2i64_v2f64
-define void @fp_to_uint_v2i64_v2f64(<2 x i64> addrspace(1)* %out, <2 x double> %in) {
- %cast = fptoui <2 x double> %in to <2 x i64>
- store <2 x i64> %cast, <2 x i64> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: @fp_to_uint_v4i64_v4f64
-define void @fp_to_uint_v4i64_v4f64(<4 x i64> addrspace(1)* %out, <4 x double> %in) {
- %cast = fptoui <4 x double> %in to <4 x i64>
- store <4 x i64> %cast, <4 x i64> addrspace(1)* %out, align 32
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fp_to_uint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_uint.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_uint.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fp_to_uint.ll (removed)
@@ -1,217 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
-
-; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i32:
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-
-; SI: v_cvt_u32_f32_e32
-; SI: s_endpgm
-define void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
- %conv = fptoui float %in to i32
- store i32 %conv, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_uint_v2f32_to_v2i32:
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_cvt_u32_f32_e32
-; SI: v_cvt_u32_f32_e32
-define void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
- %result = fptoui <2 x float> %in to <2 x i32>
- store <2 x i32> %result, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fp_to_uint_v4f32_to_v4i32:
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; SI: v_cvt_u32_f32_e32
-; SI: v_cvt_u32_f32_e32
-; SI: v_cvt_u32_f32_e32
-; SI: v_cvt_u32_f32_e32
-
-define void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %value = load <4 x float>, <4 x float> addrspace(1) * %in
- %result = fptoui <4 x float> %value to <4 x i32>
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC: {{^}}fp_to_uint_f32_to_i64:
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: s_endpgm
-define void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
- %conv = fptoui float %x to i64
- store i64 %conv, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC: {{^}}fp_to_uint_v2f32_to_v2i64:
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: s_endpgm
-define void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
- %conv = fptoui <2 x float> %x to <2 x i64>
- store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC: {{^}}fp_to_uint_v4f32_to_v4i64:
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: AND_INT
-; EG-DAG: LSHR
-; EG-DAG: SUB_INT
-; EG-DAG: AND_INT
-; EG-DAG: ASHR
-; EG-DAG: AND_INT
-; EG-DAG: OR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: LSHL
-; EG-DAG: LSHL
-; EG-DAG: SUB_INT
-; EG-DAG: LSHR
-; EG-DAG: LSHR
-; EG-DAG: SETGT_UINT
-; EG-DAG: SETGT_INT
-; EG-DAG: XOR_INT
-; EG-DAG: XOR_INT
-; EG-DAG: SUB_INT
-; EG-DAG: SUB_INT
-; EG-DAG: CNDE_INT
-; EG-DAG: CNDE_INT
-
-; SI: s_endpgm
-define void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
- %conv = fptoui <4 x float> %x to <4 x i64>
- store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fpext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fpext.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fpext.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fpext.ll (removed)
@@ -1,45 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}fpext_f32_to_f64:
-; SI: v_cvt_f64_f32_e32 {{v\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
-define void @fpext_f32_to_f64(double addrspace(1)* %out, float %in) {
- %result = fpext float %in to double
- store double %result, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fpext_v2f32_to_v2f64:
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-define void @fpext_v2f32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x float> %in) {
- %result = fpext <2 x float> %in to <2 x double>
- store <2 x double> %result, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fpext_v4f32_to_v4f64:
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-define void @fpext_v4f32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x float> %in) {
- %result = fpext <4 x float> %in to <4 x double>
- store <4 x double> %result, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fpext_v8f32_to_v8f64:
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-; SI: v_cvt_f64_f32_e32
-define void @fpext_v8f32_to_v8f64(<8 x double> addrspace(1)* %out, <8 x float> %in) {
- %result = fpext <8 x float> %in to <8 x double>
- store <8 x double> %result, <8 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fptrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fptrunc.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fptrunc.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fptrunc.ll (removed)
@@ -1,45 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}fptrunc_f64_to_f32:
-; SI: v_cvt_f32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
-define void @fptrunc_f64_to_f32(float addrspace(1)* %out, double %in) {
- %result = fptrunc double %in to float
- store float %result, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fptrunc_v2f64_to_v2f32:
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-define void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x double> %in) {
- %result = fptrunc <2 x double> %in to <2 x float>
- store <2 x float> %result, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-define void @fptrunc_v4f64_to_v4f32(<4 x float> addrspace(1)* %out, <4 x double> %in) {
- %result = fptrunc <4 x double> %in to <4 x float>
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}fptrunc_v8f64_to_v8f32:
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-; SI: v_cvt_f32_f64_e32
-define void @fptrunc_v8f64_to_v8f32(<8 x float> addrspace(1)* %out, <8 x double> %in) {
- %result = fptrunc <8 x double> %in to <8 x float>
- store <8 x float> %result, <8 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/frem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/frem.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/frem.ll (original)
+++ llvm/trunk/test/CodeGen/R600/frem.ll (removed)
@@ -1,112 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}frem_f32:
-; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
-; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
-; GCN-DAG: v_cmp
-; GCN-DAG: v_mul_f32
-; GCN: v_rcp_f32_e32
-; GCN: v_mul_f32_e32
-; GCN: v_mul_f32_e32
-; GCN: v_trunc_f32_e32
-; GCN: v_mad_f32
-; GCN: s_endpgm
-define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
- float addrspace(1)* %in2) #0 {
- %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
- %r0 = load float, float addrspace(1)* %in1, align 4
- %r1 = load float, float addrspace(1)* %gep2, align 4
- %r2 = frem float %r0, %r1
- store float %r2, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}unsafe_frem_f32:
-; GCN: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
-; GCN: buffer_load_dword [[X:v[0-9]+]], {{.*}}
-; GCN: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
-; GCN: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
-; GCN: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
-; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
-; GCN: buffer_store_dword [[RESULT]]
-; GCN: s_endpgm
-define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
- float addrspace(1)* %in2) #1 {
- %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
- %r0 = load float, float addrspace(1)* %in1, align 4
- %r1 = load float, float addrspace(1)* %gep2, align 4
- %r2 = frem float %r0, %r1
- store float %r2, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}frem_f64:
-; GCN: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
-; GCN: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
-; GCN-DAG: v_div_fmas_f64
-; GCN-DAG: v_div_scale_f64
-; GCN-DAG: v_mul_f64
-; CI: v_trunc_f64_e32
-; CI: v_mul_f64
-; GCN: v_add_f64
-; GCN: buffer_store_dwordx2
-; GCN: s_endpgm
-define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) #0 {
- %r0 = load double, double addrspace(1)* %in1, align 8
- %r1 = load double, double addrspace(1)* %in2, align 8
- %r2 = frem double %r0, %r1
- store double %r2, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}unsafe_frem_f64:
-; GCN: v_rcp_f64_e32
-; GCN: v_mul_f64
-; SI: v_bfe_u32
-; CI: v_trunc_f64_e32
-; GCN: v_fma_f64
-; GCN: s_endpgm
-define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) #1 {
- %r0 = load double, double addrspace(1)* %in1, align 8
- %r1 = load double, double addrspace(1)* %in2, align 8
- %r2 = frem double %r0, %r1
- store double %r2, double addrspace(1)* %out, align 8
- ret void
-}
-
-define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
- <2 x float> addrspace(1)* %in2) #0 {
- %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
- %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
- %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
- %r2 = frem <2 x float> %r0, %r1
- store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
- <4 x float> addrspace(1)* %in2) #0 {
- %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
- %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
- %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
- %r2 = frem <4 x float> %r0, %r1
- store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-define void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
- <2 x double> addrspace(1)* %in2) #0 {
- %gep2 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in2, i32 4
- %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1, align 16
- %r1 = load <2 x double>, <2 x double> addrspace(1)* %gep2, align 16
- %r2 = frem <2 x double> %r0, %r1
- store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-attributes #0 = { nounwind "unsafe-fp-math"="false" }
-attributes #1 = { nounwind "unsafe-fp-math"="true" }
Removed: llvm/trunk/test/CodeGen/R600/fsqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsqrt.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsqrt.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsqrt.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s
-
-; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x)
-
-; CHECK: {{^}}fsqrt_f32:
-; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
-
-define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %r0 = load float, float addrspace(1)* %in
- %r1 = call float @llvm.sqrt.f32(float %r0)
- store float %r1, float addrspace(1)* %out
- ret void
-}
-
-; CHECK: {{^}}fsqrt_f64:
-; CHECK: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
-
-define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
- %r0 = load double, double addrspace(1)* %in
- %r1 = call double @llvm.sqrt.f64(double %r0)
- store double %r1, double addrspace(1)* %out
- ret void
-}
-
-declare float @llvm.sqrt.f32(float %Val)
-declare double @llvm.sqrt.f64(double %Val)
Removed: llvm/trunk/test/CodeGen/R600/fsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsub.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsub.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsub.ll (removed)
@@ -1,75 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-
-; FUNC-LABEL: {{^}}v_fsub_f32:
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
- %a = load float, float addrspace(1)* %in, align 4
- %b = load float, float addrspace(1)* %b_ptr, align 4
- %result = fsub float %a, %b
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}s_fsub_f32:
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
-
-; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
-define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) {
- %sub = fsub float %a, %b
- store float %sub, float addrspace(1)* %out, align 4
- ret void
-}
-
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
-
-; FUNC-LABEL: {{^}}fsub_v2f32:
-; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
-; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
-
-; FIXME: Should be using SGPR directly for first operand
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
- %sub = fsub <2 x float> %a, %b
- store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_fsub_v4f32:
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
-; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
-
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
- %b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
- %result = fsub <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; FIXME: Should be using SGPR directly for first operand
-
-; FUNC-LABEL: {{^}}s_fsub_v4f32:
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: s_endpgm
-define void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
- %result = fsub <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/fsub64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsub64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsub64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsub64.ll (removed)
@@ -1,107 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare double @llvm.fabs.f64(double) #0
-
-; SI-LABEL: {{^}}fsub_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r2 = fsub double %r0, %r1
- store double %r2, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fsub_fabs_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
-define void @fsub_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r1.fabs = call double @llvm.fabs.f64(double %r1) #0
- %r2 = fsub double %r0, %r1.fabs
- store double %r2, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fsub_fabs_inv_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}
-define void @fsub_fabs_inv_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
- double addrspace(1)* %in2) {
- %r0 = load double, double addrspace(1)* %in1
- %r1 = load double, double addrspace(1)* %in2
- %r0.fabs = call double @llvm.fabs.f64(double %r0) #0
- %r2 = fsub double %r0.fabs, %r1
- store double %r2, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}s_fsub_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-define void @s_fsub_f64(double addrspace(1)* %out, double %a, double %b) {
- %sub = fsub double %a, %b
- store double %sub, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}s_fsub_imm_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], 4.0, -s\[[0-9]+:[0-9]+\]}}
-define void @s_fsub_imm_f64(double addrspace(1)* %out, double %a, double %b) {
- %sub = fsub double 4.0, %a
- store double %sub, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}s_fsub_imm_inv_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -4.0, s\[[0-9]+:[0-9]+\]}}
-define void @s_fsub_imm_inv_f64(double addrspace(1)* %out, double %a, double %b) {
- %sub = fsub double %a, 4.0
- store double %sub, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}s_fsub_self_f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}
-define void @s_fsub_self_f64(double addrspace(1)* %out, double %a) {
- %sub = fsub double %a, %a
- store double %sub, double addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fsub_v2f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-define void @fsub_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) {
- %sub = fsub <2 x double> %a, %b
- store <2 x double> %sub, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}fsub_v4f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-define void @fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x double>, <4 x double> addrspace(1)* %in, i32 1
- %a = load <4 x double>, <4 x double> addrspace(1)* %in
- %b = load <4 x double>, <4 x double> addrspace(1)* %b_ptr
- %result = fsub <4 x double> %a, %b
- store <4 x double> %result, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}s_fsub_v4f64:
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
-define void @s_fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) {
- %result = fsub <4 x double> %a, %b
- store <4 x double> %result, <4 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/ftrunc.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ftrunc.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ftrunc.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ftrunc.f64.ll (removed)
@@ -1,111 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
-
-declare double @llvm.trunc.f64(double) nounwind readnone
-declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone
-declare <3 x double> @llvm.trunc.v3f64(<3 x double>) nounwind readnone
-declare <4 x double> @llvm.trunc.v4f64(<4 x double>) nounwind readnone
-declare <8 x double> @llvm.trunc.v8f64(<8 x double>) nounwind readnone
-declare <16 x double> @llvm.trunc.v16f64(<16 x double>) nounwind readnone
-
-; FUNC-LABEL: {{^}}v_ftrunc_f64:
-; CI: v_trunc_f64
-; SI: v_bfe_u32 {{v[0-9]+}}, {{v[0-9]+}}, 20, 11
-; SI: s_endpgm
-define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
- %x = load double, double addrspace(1)* %in, align 8
- %y = call double @llvm.trunc.f64(double %x) nounwind readnone
- store double %y, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_f64:
-; CI: v_trunc_f64_e32
-
-; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
-; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
-; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
-; SI: s_lshr_b64
-; SI: s_not_b64
-; SI: s_and_b64
-; SI: cmp_gt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI: cmp_lt_i32
-; SI: cndmask_b32
-; SI: cndmask_b32
-; SI: s_endpgm
-define void @ftrunc_f64(double addrspace(1)* %out, double %x) {
- %y = call double @llvm.trunc.f64(double %x) nounwind readnone
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v2f64:
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-define void @ftrunc_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
- %y = call <2 x double> @llvm.trunc.v2f64(<2 x double> %x) nounwind readnone
- store <2 x double> %y, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; FIXME-FUNC-LABEL: {{^}}ftrunc_v3f64:
-; FIXME-CI: v_trunc_f64_e32
-; FIXME-CI: v_trunc_f64_e32
-; FIXME-CI: v_trunc_f64_e32
-; define void @ftrunc_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
-; %y = call <3 x double> @llvm.trunc.v3f64(<3 x double> %x) nounwind readnone
-; store <3 x double> %y, <3 x double> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}ftrunc_v4f64:
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-define void @ftrunc_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
- %y = call <4 x double> @llvm.trunc.v4f64(<4 x double> %x) nounwind readnone
- store <4 x double> %y, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v8f64:
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-define void @ftrunc_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
- %y = call <8 x double> @llvm.trunc.v8f64(<8 x double> %x) nounwind readnone
- store <8 x double> %y, <8 x double> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v16f64:
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-; CI: v_trunc_f64_e32
-define void @ftrunc_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
- %y = call <16 x double> @llvm.trunc.v16f64(<16 x double> %x) nounwind readnone
- store <16 x double> %y, <16 x double> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/ftrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ftrunc.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ftrunc.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ftrunc.ll (removed)
@@ -1,120 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG --check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s
-
-declare float @llvm.trunc.f32(float) nounwind readnone
-declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone
-declare <3 x float> @llvm.trunc.v3f32(<3 x float>) nounwind readnone
-declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone
-declare <8 x float> @llvm.trunc.v8f32(<8 x float>) nounwind readnone
-declare <16 x float> @llvm.trunc.v16f32(<16 x float>) nounwind readnone
-
-; FUNC-LABEL: {{^}}ftrunc_f32:
-; EG: TRUNC
-; SI: v_trunc_f32_e32
-define void @ftrunc_f32(float addrspace(1)* %out, float %x) {
- %y = call float @llvm.trunc.f32(float %x) nounwind readnone
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v2f32:
-; EG: TRUNC
-; EG: TRUNC
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-define void @ftrunc_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) {
- %y = call <2 x float> @llvm.trunc.v2f32(<2 x float> %x) nounwind readnone
- store <2 x float> %y, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; FIXME-FUNC-LABEL: {{^}}ftrunc_v3f32:
-; FIXME-EG: TRUNC
-; FIXME-EG: TRUNC
-; FIXME-EG: TRUNC
-; FIXME-SI: v_trunc_f32_e32
-; FIXME-SI: v_trunc_f32_e32
-; FIXME-SI: v_trunc_f32_e32
-; define void @ftrunc_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) {
-; %y = call <3 x float> @llvm.trunc.v3f32(<3 x float> %x) nounwind readnone
-; store <3 x float> %y, <3 x float> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}ftrunc_v4f32:
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-define void @ftrunc_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) {
- %y = call <4 x float> @llvm.trunc.v4f32(<4 x float> %x) nounwind readnone
- store <4 x float> %y, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v8f32:
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-define void @ftrunc_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) {
- %y = call <8 x float> @llvm.trunc.v8f32(<8 x float> %x) nounwind readnone
- store <8 x float> %y, <8 x float> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}ftrunc_v16f32:
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; EG: TRUNC
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-; SI: v_trunc_f32_e32
-define void @ftrunc_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %x) {
- %y = call <16 x float> @llvm.trunc.v16f32(<16 x float> %x) nounwind readnone
- store <16 x float> %y, <16 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/gep-address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/gep-address-space.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/gep-address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/gep-address-space.ll (removed)
@@ -1,55 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
-
-define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
-; CHECK-LABEL: {{^}}use_gep_address_space:
-; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
-; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64
- %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16
- store i32 99, i32 addrspace(3)* %p
- ret void
-}
-
-define void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %array) nounwind {
-; CHECK-LABEL: {{^}}use_gep_address_space_large_offset:
-; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
-; SI, which is why it is being OR'd with the base pointer.
-; SI: s_or_b32
-; CI: s_add_i32
-; CHECK: ds_write_b32
- %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
- store i32 99, i32 addrspace(3)* %p
- ret void
-}
-
-define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind {
-; CHECK-LABEL: {{^}}gep_as_vector_v4:
-; CHECK: s_add_i32
-; CHECK: s_add_i32
-; CHECK: s_add_i32
-; CHECK: s_add_i32
- %p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
- %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0
- %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1
- %p2 = extractelement <4 x i32 addrspace(3)*> %p, i32 2
- %p3 = extractelement <4 x i32 addrspace(3)*> %p, i32 3
- store i32 99, i32 addrspace(3)* %p0
- store i32 99, i32 addrspace(3)* %p1
- store i32 99, i32 addrspace(3)* %p2
- store i32 99, i32 addrspace(3)* %p3
- ret void
-}
-
-define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind {
-; CHECK-LABEL: {{^}}gep_as_vector_v2:
-; CHECK: s_add_i32
-; CHECK: s_add_i32
- %p = getelementptr [1024 x i32], <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
- %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0
- %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1
- store i32 99, i32 addrspace(3)* %p0
- store i32 99, i32 addrspace(3)* %p1
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/global-directive.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-directive.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-directive.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-directive.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; Make sure the GlobalDirective isn't merged with the function name
-
-; SI: .globl foo
-; SI: {{^}}foo:
-define void @foo(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
- %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %a = load i32, i32 addrspace(1)* %in
- %b = load i32, i32 addrspace(1)* %b_ptr
- %result = add i32 %a, %b
- store i32 %result, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/global-extload-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-extload-i1.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-extload-i1.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-extload-i1.ll (removed)
@@ -1,302 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; FIXME: Evergreen broken
-
-; FUNC-LABEL: {{^}}zextload_global_i1_to_i32:
-; SI: buffer_load_ubyte
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @zextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
- %a = load i1, i1 addrspace(1)* %in
- %ext = zext i1 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i1_to_i32:
-; SI: buffer_load_ubyte
-; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}}
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @sextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
- %a = load i1, i1 addrspace(1)* %in
- %ext = sext i1 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i32:
-; SI: s_endpgm
-define void @zextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
- %ext = zext <1 x i1> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i32:
-; SI: s_endpgm
-define void @sextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
- %ext = sext <1 x i1> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i32:
-; SI: s_endpgm
-define void @zextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
- %ext = zext <2 x i1> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i32:
-; SI: s_endpgm
-define void @sextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
- %ext = sext <2 x i1> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i32:
-; SI: s_endpgm
-define void @zextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
- %ext = zext <4 x i1> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i32:
-; SI: s_endpgm
-define void @sextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
- %ext = sext <4 x i1> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i32:
-; SI: s_endpgm
-define void @zextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
- %ext = zext <8 x i1> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i32:
-; SI: s_endpgm
-define void @sextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
- %ext = sext <8 x i1> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i32:
-; SI: s_endpgm
-define void @zextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
- %ext = zext <16 x i1> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i32:
-; SI: s_endpgm
-define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
- %ext = sext <16 x i1> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i32:
-; XSI: s_endpgm
-; define void @zextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
-; %ext = zext <32 x i1> %load to <32 x i32>
-; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i32:
-; XSI: s_endpgm
-; define void @sextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
-; %ext = sext <32 x i1> %load to <32 x i32>
-; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i32:
-; XSI: s_endpgm
-; define void @zextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
-; %ext = zext <64 x i1> %load to <64 x i32>
-; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i32:
-; XSI: s_endpgm
-; define void @sextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
-; %ext = sext <64 x i1> %load to <64 x i32>
-; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}zextload_global_i1_to_i64:
-; SI: buffer_load_ubyte [[LOAD:v[0-9]+]],
-; SI: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}}
-; SI: buffer_store_dwordx2
-define void @zextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
- %a = load i1, i1 addrspace(1)* %in
- %ext = zext i1 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i1_to_i64:
-; SI: buffer_load_ubyte [[LOAD:v[0-9]+]],
-; SI: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
-; SI: buffer_store_dwordx2
-define void @sextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind {
- %a = load i1, i1 addrspace(1)* %in
- %ext = sext i1 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i64:
-; SI: s_endpgm
-define void @zextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
- %ext = zext <1 x i1> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i64:
-; SI: s_endpgm
-define void @sextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i1>, <1 x i1> addrspace(1)* %in
- %ext = sext <1 x i1> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i64:
-; SI: s_endpgm
-define void @zextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
- %ext = zext <2 x i1> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i64:
-; SI: s_endpgm
-define void @sextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i1>, <2 x i1> addrspace(1)* %in
- %ext = sext <2 x i1> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i64:
-; SI: s_endpgm
-define void @zextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
- %ext = zext <4 x i1> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i64:
-; SI: s_endpgm
-define void @sextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i1>, <4 x i1> addrspace(1)* %in
- %ext = sext <4 x i1> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i64:
-; SI: s_endpgm
-define void @zextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
- %ext = zext <8 x i1> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i64:
-; SI: s_endpgm
-define void @sextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i1>, <8 x i1> addrspace(1)* %in
- %ext = sext <8 x i1> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i64:
-; SI: s_endpgm
-define void @zextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
- %ext = zext <16 x i1> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i64:
-; SI: s_endpgm
-define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i1>, <16 x i1> addrspace(1)* %in
- %ext = sext <16 x i1> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i64:
-; XSI: s_endpgm
-; define void @zextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
-; %ext = zext <32 x i1> %load to <32 x i64>
-; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i64:
-; XSI: s_endpgm
-; define void @sextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in
-; %ext = sext <32 x i1> %load to <32 x i64>
-; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i64:
-; XSI: s_endpgm
-; define void @zextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
-; %ext = zext <64 x i1> %load to <64 x i64>
-; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i64:
-; XSI: s_endpgm
-; define void @sextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in
-; %ext = sext <64 x i1> %load to <64 x i64>
-; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
-; ret void
-; }
Removed: llvm/trunk/test/CodeGen/R600/global-extload-i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-extload-i16.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-extload-i16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-extload-i16.ll (removed)
@@ -1,302 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; FIXME: cypress is broken because the bigger testcases spill and it's not implemented
-
-; FUNC-LABEL: {{^}}zextload_global_i16_to_i32:
-; SI: buffer_load_ushort
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @zextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
- %a = load i16, i16 addrspace(1)* %in
- %ext = zext i16 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i16_to_i32:
-; SI: buffer_load_sshort
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @sextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
- %a = load i16, i16 addrspace(1)* %in
- %ext = sext i16 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i16_to_v1i32:
-; SI: buffer_load_ushort
-; SI: s_endpgm
-define void @zextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
- %ext = zext <1 x i16> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i16_to_v1i32:
-; SI: buffer_load_sshort
-; SI: s_endpgm
-define void @sextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
- %ext = sext <1 x i16> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i32:
-; SI: s_endpgm
-define void @zextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
- %ext = zext <2 x i16> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i32:
-; SI: s_endpgm
-define void @sextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
- %ext = sext <2 x i16> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i32:
-; SI: s_endpgm
-define void @zextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
- %ext = zext <4 x i16> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i32:
-; SI: s_endpgm
-define void @sextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
- %ext = sext <4 x i16> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i32:
-; SI: s_endpgm
-define void @zextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
- %ext = zext <8 x i16> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i32:
-; SI: s_endpgm
-define void @sextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
- %ext = sext <8 x i16> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i32:
-; SI: s_endpgm
-define void @zextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
- %ext = zext <16 x i16> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i32:
-; SI: s_endpgm
-define void @sextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
- %ext = sext <16 x i16> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i32:
-; SI: s_endpgm
-define void @zextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
- %ext = zext <32 x i16> %load to <32 x i32>
- store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i32:
-; SI: s_endpgm
-define void @sextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
- %ext = sext <32 x i16> %load to <32 x i32>
- store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i32:
-; SI: s_endpgm
-define void @zextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
- %ext = zext <64 x i16> %load to <64 x i32>
- store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i32:
-; SI: s_endpgm
-define void @sextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
- %ext = sext <64 x i16> %load to <64 x i32>
- store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_i16_to_i64:
-; SI: buffer_load_ushort v[[LO:[0-9]+]],
-; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
-; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
-define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
- %a = load i16, i16 addrspace(1)* %in
- %ext = zext i16 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i16_to_i64:
-; SI: buffer_load_sshort [[LOAD:v[0-9]+]],
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
-; SI: buffer_store_dwordx2
-define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind {
- %a = load i16, i16 addrspace(1)* %in
- %ext = sext i16 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i16_to_v1i64:
-; SI: s_endpgm
-define void @zextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
- %ext = zext <1 x i16> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i16_to_v1i64:
-; SI: s_endpgm
-define void @sextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i16>, <1 x i16> addrspace(1)* %in
- %ext = sext <1 x i16> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i64:
-; SI: s_endpgm
-define void @zextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
- %ext = zext <2 x i16> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i64:
-; SI: s_endpgm
-define void @sextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i16>, <2 x i16> addrspace(1)* %in
- %ext = sext <2 x i16> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i64:
-; SI: s_endpgm
-define void @zextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
- %ext = zext <4 x i16> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i64:
-; SI: s_endpgm
-define void @sextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i16>, <4 x i16> addrspace(1)* %in
- %ext = sext <4 x i16> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i64:
-; SI: s_endpgm
-define void @zextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
- %ext = zext <8 x i16> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i64:
-; SI: s_endpgm
-define void @sextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i16>, <8 x i16> addrspace(1)* %in
- %ext = sext <8 x i16> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i64:
-; SI: s_endpgm
-define void @zextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
- %ext = zext <16 x i16> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i64:
-; SI: s_endpgm
-define void @sextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i16>, <16 x i16> addrspace(1)* %in
- %ext = sext <16 x i16> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i64:
-; SI: s_endpgm
-define void @zextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
- %ext = zext <32 x i16> %load to <32 x i64>
- store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i64:
-; SI: s_endpgm
-define void @sextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i16>, <32 x i16> addrspace(1)* %in
- %ext = sext <32 x i16> %load to <32 x i64>
- store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i64:
-; SI: s_endpgm
-define void @zextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
- %ext = zext <64 x i16> %load to <64 x i64>
- store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i64:
-; SI: s_endpgm
-define void @sextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind {
- %load = load <64 x i16>, <64 x i16> addrspace(1)* %in
- %ext = sext <64 x i16> %load to <64 x i64>
- store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/global-extload-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-extload-i32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-extload-i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-extload-i32.ll (removed)
@@ -1,457 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}zextload_global_i32_to_i64:
-; SI: buffer_load_dword v[[LO:[0-9]+]],
-; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
-; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
-define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %a = load i32, i32 addrspace(1)* %in
- %ext = zext i32 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i32_to_i64:
-; SI: buffer_load_dword [[LOAD:v[0-9]+]],
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
-; SI: buffer_store_dwordx2
-define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %a = load i32, i32 addrspace(1)* %in
- %ext = sext i32 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i32_to_v1i64:
-; SI: buffer_load_dword
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @zextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i32>, <1 x i32> addrspace(1)* %in
- %ext = zext <1 x i32> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i32_to_v1i64:
-; SI: buffer_load_dword
-; SI: v_ashrrev_i32
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @sextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i32>, <1 x i32> addrspace(1)* %in
- %ext = sext <1 x i32> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i32_to_v2i64:
-; SI: buffer_load_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @zextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i32>, <2 x i32> addrspace(1)* %in
- %ext = zext <2 x i32> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i32_to_v2i64:
-; SI: buffer_load_dwordx2
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI: s_endpgm
-define void @sextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i32>, <2 x i32> addrspace(1)* %in
- %ext = sext <2 x i32> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i32_to_v4i64:
-; SI: buffer_load_dwordx4
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @zextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i32>, <4 x i32> addrspace(1)* %in
- %ext = zext <4 x i32> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i32_to_v4i64:
-; SI: buffer_load_dwordx4
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI: s_endpgm
-define void @sextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i32>, <4 x i32> addrspace(1)* %in
- %ext = sext <4 x i32> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i32_to_v8i64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI: s_endpgm
-define void @zextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i32>, <8 x i32> addrspace(1)* %in
- %ext = zext <8 x i32> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i32_to_v8i64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI: s_endpgm
-define void @sextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i32>, <8 x i32> addrspace(1)* %in
- %ext = sext <8 x i32> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i32_to_v16i64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI: s_endpgm
-define void @sextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i32>, <16 x i32> addrspace(1)* %in
- %ext = sext <16 x i32> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i32_to_v16i64
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-
-; SI: s_endpgm
-define void @zextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i32>, <16 x i32> addrspace(1)* %in
- %ext = zext <16 x i32> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v32i32_to_v32i64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-; SI-DAG: v_ashrrev_i32
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI: s_endpgm
-define void @sextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i32>, <32 x i32> addrspace(1)* %in
- %ext = sext <32 x i32> %load to <32 x i64>
- store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v32i32_to_v32i64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-; SI: buffer_load_dword
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-; SI-DAG: buffer_store_dwordx2
-
-; SI: s_endpgm
-define void @zextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind {
- %load = load <32 x i32>, <32 x i32> addrspace(1)* %in
- %ext = zext <32 x i32> %load to <32 x i64>
- store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/global-extload-i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-extload-i8.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-extload-i8.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-extload-i8.ll (removed)
@@ -1,299 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}zextload_global_i8_to_i32:
-; SI: buffer_load_ubyte
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @zextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
- %a = load i8, i8 addrspace(1)* %in
- %ext = zext i8 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i8_to_i32:
-; SI: buffer_load_sbyte
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @sextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
- %a = load i8, i8 addrspace(1)* %in
- %ext = sext i8 %a to i32
- store i32 %ext, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i32:
-; SI: s_endpgm
-define void @zextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
- %ext = zext <1 x i8> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i32:
-; SI: s_endpgm
-define void @sextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
- %ext = sext <1 x i8> %load to <1 x i32>
- store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i32:
-; SI: s_endpgm
-define void @zextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
- %ext = zext <2 x i8> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i32:
-; SI: s_endpgm
-define void @sextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
- %ext = sext <2 x i8> %load to <2 x i32>
- store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i32:
-; SI: s_endpgm
-define void @zextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
- %ext = zext <4 x i8> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i32:
-; SI: s_endpgm
-define void @sextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
- %ext = sext <4 x i8> %load to <4 x i32>
- store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i32:
-; SI: s_endpgm
-define void @zextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
- %ext = zext <8 x i8> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i32:
-; SI: s_endpgm
-define void @sextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
- %ext = sext <8 x i8> %load to <8 x i32>
- store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i32:
-; SI: s_endpgm
-define void @zextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
- %ext = zext <16 x i8> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i32:
-; SI: s_endpgm
-define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
- %ext = sext <16 x i8> %load to <16 x i32>
- store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
- ret void
-}
-
-; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i32:
-; XSI: s_endpgm
-; define void @zextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
-; %ext = zext <32 x i8> %load to <32 x i32>
-; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i32:
-; XSI: s_endpgm
-; define void @sextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
-; %ext = sext <32 x i8> %load to <32 x i32>
-; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i32:
-; XSI: s_endpgm
-; define void @zextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
-; %ext = zext <64 x i8> %load to <64 x i32>
-; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i32:
-; XSI: s_endpgm
-; define void @sextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
-; %ext = sext <64 x i8> %load to <64 x i32>
-; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
-; ret void
-; }
-
-; FUNC-LABEL: {{^}}zextload_global_i8_to_i64:
-; SI: buffer_load_ubyte v[[LO:[0-9]+]],
-; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
-; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
-define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
- %a = load i8, i8 addrspace(1)* %in
- %ext = zext i8 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_i8_to_i64:
-; SI: buffer_load_sbyte [[LOAD:v[0-9]+]],
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
-; SI: buffer_store_dwordx2
-define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
- %a = load i8, i8 addrspace(1)* %in
- %ext = sext i8 %a to i64
- store i64 %ext, i64 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i64:
-; SI: s_endpgm
-define void @zextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
- %ext = zext <1 x i8> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i64:
-; SI: s_endpgm
-define void @sextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <1 x i8>, <1 x i8> addrspace(1)* %in
- %ext = sext <1 x i8> %load to <1 x i64>
- store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i64:
-; SI: s_endpgm
-define void @zextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
- %ext = zext <2 x i8> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i64:
-; SI: s_endpgm
-define void @sextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <2 x i8>, <2 x i8> addrspace(1)* %in
- %ext = sext <2 x i8> %load to <2 x i64>
- store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i64:
-; SI: s_endpgm
-define void @zextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
- %ext = zext <4 x i8> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i64:
-; SI: s_endpgm
-define void @sextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <4 x i8>, <4 x i8> addrspace(1)* %in
- %ext = sext <4 x i8> %load to <4 x i64>
- store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i64:
-; SI: s_endpgm
-define void @zextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
- %ext = zext <8 x i8> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i64:
-; SI: s_endpgm
-define void @sextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <8 x i8>, <8 x i8> addrspace(1)* %in
- %ext = sext <8 x i8> %load to <8 x i64>
- store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i64:
-; SI: s_endpgm
-define void @zextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
- %ext = zext <16 x i8> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i64:
-; SI: s_endpgm
-define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind {
- %load = load <16 x i8>, <16 x i8> addrspace(1)* %in
- %ext = sext <16 x i8> %load to <16 x i64>
- store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
- ret void
-}
-
-; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i64:
-; XSI: s_endpgm
-; define void @zextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
-; %ext = zext <32 x i8> %load to <32 x i64>
-; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i64:
-; XSI: s_endpgm
-; define void @sextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in
-; %ext = sext <32 x i8> %load to <32 x i64>
-; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i64:
-; XSI: s_endpgm
-; define void @zextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
-; %ext = zext <64 x i8> %load to <64 x i64>
-; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
-; ret void
-; }
-
-; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i64:
-; XSI: s_endpgm
-; define void @sextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind {
-; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in
-; %ext = sext <64 x i8> %load to <64 x i64>
-; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
-; ret void
-; }
Removed: llvm/trunk/test/CodeGen/R600/global-zero-initializer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global-zero-initializer.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global-zero-initializer.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global-zero-initializer.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s
-; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
-
-; CHECK: error: unsupported initializer for address space in load_init_global_global
-
- at lds = addrspace(1) global [256 x i32] zeroinitializer
-
-define void @load_init_global_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [256 x i32], [256 x i32] addrspace(1)* @lds, i32 0, i32 10
- %ld = load i32, i32 addrspace(1)* %gep
- store i32 %ld, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/global_atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/global_atomics.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/global_atomics.ll (original)
+++ llvm/trunk/test/CodeGen/R600/global_atomics.ll (removed)
@@ -1,801 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}atomic_add_i32_offset:
-; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_ret_offset:
-; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset:
-; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64_offset:
-; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32:
-; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_ret:
-; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_add_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_addr64:
-; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64:
-; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_offset:
-; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_ret_offset:
-; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset:
-; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64_offset:
-; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32:
-; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_ret:
-; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_and_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_addr64:
-; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64:
-; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_offset:
-; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_ret_offset:
-; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset:
-; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset:
-; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32:
-; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_ret:
-; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_sub_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_addr64:
-; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64:
-; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_offset:
-; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_ret_offset:
-; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset:
-; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64_offset:
-; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32:
-; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_ret:
-; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_max_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_addr64:
-; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64:
-; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_offset:
-; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_ret_offset:
-; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset:
-; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset:
-; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32:
-; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_ret:
-; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umax_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_addr64:
-; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64:
-; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_offset:
-; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_ret_offset:
-; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset:
-; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64_offset:
-; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32:
-; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_ret:
-; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_min_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_addr64:
-; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64:
-; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_offset:
-; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_ret_offset:
-; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset:
-; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset:
-; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32:
-; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_ret:
-; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umin_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_addr64:
-; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64:
-; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_offset:
-; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_ret_offset:
-; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset:
-; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64_offset:
-; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32:
-; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_ret:
-; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_or_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_addr64:
-; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64:
-; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_offset:
-; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_offset:
-; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64_offset:
-; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset:
-; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32:
-; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_ret:
-; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64:
-; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64:
-; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_offset:
-; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
-define void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_ret_offset:
-; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4
- %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset:
-; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
-define void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset:
-; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
- %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32:
-; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
-define void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_ret:
-; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xor_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) {
-entry:
- %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_addr64:
-; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
-define void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst
- ret void
-}
-
-; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64:
-; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
-; SI: buffer_store_dword [[RET]]
-define void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) {
-entry:
- %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index
- %0 = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst
- store i32 %0, i32 addrspace(1)* %out2
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/gv-const-addrspace-fail.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/gv-const-addrspace-fail.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/gv-const-addrspace-fail.ll (original)
+++ llvm/trunk/test/CodeGen/R600/gv-const-addrspace-fail.ll (removed)
@@ -1,57 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-
- at a = internal addrspace(2) constant [1 x i8] [ i8 7 ], align 1
-
-; FUNC-LABEL: {{^}}test_i8:
-; EG: CF_END
-; SI: buffer_store_byte
-; SI: s_endpgm
-define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 {
- %arrayidx = getelementptr inbounds [1 x i8], [1 x i8] addrspace(2)* @a, i32 0, i32 %s
- %1 = load i8, i8 addrspace(2)* %arrayidx, align 1
- store i8 %1, i8 addrspace(1)* %out
- ret void
-}
-
- at b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2
-
-; FUNC-LABEL: {{^}}test_i16:
-; EG: CF_END
-; SI: buffer_store_short
-; SI: s_endpgm
-define void @test_i16( i32 %s, i16 addrspace(1)* %out) #3 {
- %arrayidx = getelementptr inbounds [1 x i16], [1 x i16] addrspace(2)* @b, i32 0, i32 %s
- %1 = load i16, i16 addrspace(2)* %arrayidx, align 2
- store i16 %1, i16 addrspace(1)* %out
- ret void
-}
-
-%struct.bar = type { float, [5 x i8] }
-
-; The illegal i8s aren't handled
- at struct_bar_gv = internal addrspace(2) constant [1 x %struct.bar] [ %struct.bar { float 16.0, [5 x i8] [i8 0, i8 1, i8 2, i8 3, i8 4] } ]
-
-; FUNC-LABEL: {{^}}struct_bar_gv_load:
-define void @struct_bar_gv_load(i8 addrspace(1)* %out, i32 %index) {
- %gep = getelementptr inbounds [1 x %struct.bar], [1 x %struct.bar] addrspace(2)* @struct_bar_gv, i32 0, i32 0, i32 1, i32 %index
- %load = load i8, i8 addrspace(2)* %gep, align 1
- store i8 %load, i8 addrspace(1)* %out, align 1
- ret void
-}
-
-
-; The private load isn't scalarzied.
- at array_vector_gv = internal addrspace(2) constant [4 x <4 x i32>] [ <4 x i32> <i32 1, i32 2, i32 3, i32 4>,
- <4 x i32> <i32 5, i32 6, i32 7, i32 8>,
- <4 x i32> <i32 9, i32 10, i32 11, i32 12>,
- <4 x i32> <i32 13, i32 14, i32 15, i32 16> ]
-
-; FUNC-LABEL: {{^}}array_vector_gv_load:
-define void @array_vector_gv_load(<4 x i32> addrspace(1)* %out, i32 %index) {
- %gep = getelementptr inbounds [4 x <4 x i32>], [4 x <4 x i32>] addrspace(2)* @array_vector_gv, i32 0, i32 %index
- %load = load <4 x i32>, <4 x i32> addrspace(2)* %gep, align 16
- store <4 x i32> %load, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/gv-const-addrspace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/gv-const-addrspace.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/gv-const-addrspace.ll (original)
+++ llvm/trunk/test/CodeGen/R600/gv-const-addrspace.ll (removed)
@@ -1,101 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-
- at b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2
-
- at float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4
-
-; FUNC-LABEL: {{^}}float:
-; FIXME: We should be using s_load_dword here.
-; SI: buffer_load_dword
-; VI: s_load_dword
-
-; EG-DAG: MOV {{\** *}}T2.X
-; EG-DAG: MOV {{\** *}}T3.X
-; EG-DAG: MOV {{\** *}}T4.X
-; EG-DAG: MOV {{\** *}}T5.X
-; EG-DAG: MOV {{\** *}}T6.X
-; EG: MOVA_INT
-
-define void @float(float addrspace(1)* %out, i32 %index) {
-entry:
- %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
- %1 = load float, float addrspace(2)* %0
- store float %1, float addrspace(1)* %out
- ret void
-}
-
- at i32_gv = internal unnamed_addr addrspace(2) constant [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4], align 4
-
-; FUNC-LABEL: {{^}}i32:
-
-; FIXME: We should be using s_load_dword here.
-; SI: buffer_load_dword
-; VI: s_load_dword
-
-; EG-DAG: MOV {{\** *}}T2.X
-; EG-DAG: MOV {{\** *}}T3.X
-; EG-DAG: MOV {{\** *}}T4.X
-; EG-DAG: MOV {{\** *}}T5.X
-; EG-DAG: MOV {{\** *}}T6.X
-; EG: MOVA_INT
-
-define void @i32(i32 addrspace(1)* %out, i32 %index) {
-entry:
- %0 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index
- %1 = load i32, i32 addrspace(2)* %0
- store i32 %1, i32 addrspace(1)* %out
- ret void
-}
-
-
-%struct.foo = type { float, [5 x i32] }
-
- at struct_foo_gv = internal unnamed_addr addrspace(2) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ]
-
-; FUNC-LABEL: {{^}}struct_foo_gv_load:
-; GCN: s_load_dword
-
-define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
- %gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
- %load = load i32, i32 addrspace(2)* %gep, align 4
- store i32 %load, i32 addrspace(1)* %out, align 4
- ret void
-}
-
- at array_v1_gv = internal addrspace(2) constant [4 x <1 x i32>] [ <1 x i32> <i32 1>,
- <1 x i32> <i32 2>,
- <1 x i32> <i32 3>,
- <1 x i32> <i32 4> ]
-
-; FUNC-LABEL: {{^}}array_v1_gv_load:
-; FIXME: We should be using s_load_dword here.
-; SI: buffer_load_dword
-; VI: s_load_dword
-define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
- %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
- %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4
- store <1 x i32> %load, <1 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-define void @gv_addressing_in_branch(float addrspace(1)* %out, i32 %index, i32 %a) {
-entry:
- %0 = icmp eq i32 0, %a
- br i1 %0, label %if, label %else
-
-if:
- %1 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
- %2 = load float, float addrspace(2)* %1
- store float %2, float addrspace(1)* %out
- br label %endif
-
-else:
- store float 1.0, float addrspace(1)* %out
- br label %endif
-
-endif:
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/half.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/half.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/half.ll (original)
+++ llvm/trunk/test/CodeGen/R600/half.ll (removed)
@@ -1,525 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-
-; half args should be promoted to float
-
-; GCN-LABEL: {{^}}load_f16_arg:
-; GCN: s_load_dword [[ARG:s[0-9]+]]
-; GCN: v_cvt_f16_f32_e32 [[CVT:v[0-9]+]], [[ARG]]
-; GCN: buffer_store_short [[CVT]]
-define void @load_f16_arg(half addrspace(1)* %out, half %arg) #0 {
- store half %arg, half addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}load_v2f16_arg:
-; GCN-DAG: buffer_load_ushort [[V0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44
-; GCN-DAG: buffer_load_ushort [[V1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46
-; GCN-DAG: buffer_store_short [[V0]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
-; GCN-DAG: buffer_store_short [[V1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}}
-; GCN: s_endpgm
-define void @load_v2f16_arg(<2 x half> addrspace(1)* %out, <2 x half> %arg) #0 {
- store <2 x half> %arg, <2 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}load_v3f16_arg:
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN-NOT: buffer_load
-; GCN-DAG: buffer_store_dword
-; GCN-DAG: buffer_store_short
-; GCN-NOT: buffer_store
-; GCN: s_endpgm
-define void @load_v3f16_arg(<3 x half> addrspace(1)* %out, <3 x half> %arg) #0 {
- store <3 x half> %arg, <3 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}load_v4f16_arg:
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: s_endpgm
-define void @load_v4f16_arg(<4 x half> addrspace(1)* %out, <4 x half> %arg) #0 {
- store <4 x half> %arg, <4 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}load_v8f16_arg:
-define void @load_v8f16_arg(<8 x half> addrspace(1)* %out, <8 x half> %arg) #0 {
- store <8 x half> %arg, <8 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v2f16_arg:
-define void @extload_v2f16_arg(<2 x float> addrspace(1)* %out, <2 x half> %in) #0 {
- %fpext = fpext <2 x half> %in to <2 x float>
- store <2 x float> %fpext, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_f16_to_f32_arg:
-define void @extload_f16_to_f32_arg(float addrspace(1)* %out, half %arg) #0 {
- %ext = fpext half %arg to float
- store float %ext, float addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v2f16_to_v2f32_arg:
-define void @extload_v2f16_to_v2f32_arg(<2 x float> addrspace(1)* %out, <2 x half> %arg) #0 {
- %ext = fpext <2 x half> %arg to <2 x float>
- store <2 x float> %ext, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v3f16_to_v3f32_arg:
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN-NOT: buffer_load
-; GCN: v_cvt_f32_f16_e32
-; GCN: v_cvt_f32_f16_e32
-; GCN: v_cvt_f32_f16_e32
-; GCN-NOT: v_cvt_f32_f16
-; GCN-DAG: buffer_store_dword
-; GCN-DAG: buffer_store_dwordx2
-; GCN: s_endpgm
-define void @extload_v3f16_to_v3f32_arg(<3 x float> addrspace(1)* %out, <3 x half> %arg) #0 {
- %ext = fpext <3 x half> %arg to <3 x float>
- store <3 x float> %ext, <3 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v4f16_to_v4f32_arg:
-define void @extload_v4f16_to_v4f32_arg(<4 x float> addrspace(1)* %out, <4 x half> %arg) #0 {
- %ext = fpext <4 x half> %arg to <4 x float>
- store <4 x float> %ext, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v8f16_to_v8f32_arg:
-define void @extload_v8f16_to_v8f32_arg(<8 x float> addrspace(1)* %out, <8 x half> %arg) #0 {
- %ext = fpext <8 x half> %arg to <8 x float>
- store <8 x float> %ext, <8 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_f16_to_f64_arg:
-define void @extload_f16_to_f64_arg(double addrspace(1)* %out, half %arg) #0 {
- %ext = fpext half %arg to double
- store double %ext, double addrspace(1)* %out
- ret void
-}
-; GCN-LABEL: {{^}}extload_v2f16_to_v2f64_arg:
-define void @extload_v2f16_to_v2f64_arg(<2 x double> addrspace(1)* %out, <2 x half> %arg) #0 {
- %ext = fpext <2 x half> %arg to <2 x double>
- store <2 x double> %ext, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v3f16_to_v3f64_arg:
-define void @extload_v3f16_to_v3f64_arg(<3 x double> addrspace(1)* %out, <3 x half> %arg) #0 {
- %ext = fpext <3 x half> %arg to <3 x double>
- store <3 x double> %ext, <3 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v4f16_to_v4f64_arg:
-define void @extload_v4f16_to_v4f64_arg(<4 x double> addrspace(1)* %out, <4 x half> %arg) #0 {
- %ext = fpext <4 x half> %arg to <4 x double>
- store <4 x double> %ext, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}extload_v8f16_to_v8f64_arg:
-define void @extload_v8f16_to_v8f64_arg(<8 x double> addrspace(1)* %out, <8 x half> %arg) #0 {
- %ext = fpext <8 x half> %arg to <8 x double>
- store <8 x double> %ext, <8 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_load_store_f16:
-; GCN: buffer_load_ushort [[TMP:v[0-9]+]]
-; GCN: buffer_store_short [[TMP]]
-define void @global_load_store_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 {
- %val = load half, half addrspace(1)* %in
- store half %val, half addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_load_store_v2f16:
-; GCN: buffer_load_dword [[TMP:v[0-9]+]]
-; GCN: buffer_store_dword [[TMP]]
-define void @global_load_store_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
- %val = load <2 x half>, <2 x half> addrspace(1)* %in
- store <2 x half> %val, <2 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_load_store_v4f16:
-; GCN: buffer_load_dwordx2 [[TMP:v\[[0-9]+:[0-9]+\]]]
-; GCN: buffer_store_dwordx2 [[TMP]]
-define void @global_load_store_v4f16(<4 x half> addrspace(1)* %in, <4 x half> addrspace(1)* %out) #0 {
- %val = load <4 x half>, <4 x half> addrspace(1)* %in
- store <4 x half> %val, <4 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_load_store_v8f16:
-; GCN: buffer_load_dwordx4 [[TMP:v\[[0-9]+:[0-9]+\]]]
-; GCN: buffer_store_dwordx4 [[TMP:v\[[0-9]+:[0-9]+\]]]
-; GCN: s_endpgm
-define void @global_load_store_v8f16(<8 x half> addrspace(1)* %out, <8 x half> addrspace(1)* %in) #0 {
- %val = load <8 x half>, <8 x half> addrspace(1)* %in
- store <8 x half> %val, <8 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_f16_to_f32:
-; GCN: buffer_load_ushort [[LOAD:v[0-9]+]]
-; GCN: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[LOAD]]
-; GCN: buffer_store_dword [[CVT]]
-define void @global_extload_f16_to_f32(float addrspace(1)* %out, half addrspace(1)* %in) #0 {
- %val = load half, half addrspace(1)* %in
- %cvt = fpext half %val to float
- store float %cvt, float addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v2f16_to_v2f32:
-define void @global_extload_v2f16_to_v2f32(<2 x float> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
- %val = load <2 x half>, <2 x half> addrspace(1)* %in
- %cvt = fpext <2 x half> %val to <2 x float>
- store <2 x float> %cvt, <2 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f32:
-define void @global_extload_v3f16_to_v3f32(<3 x float> addrspace(1)* %out, <3 x half> addrspace(1)* %in) #0 {
- %val = load <3 x half>, <3 x half> addrspace(1)* %in
- %cvt = fpext <3 x half> %val to <3 x float>
- store <3 x float> %cvt, <3 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v4f16_to_v4f32:
-define void @global_extload_v4f16_to_v4f32(<4 x float> addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
- %val = load <4 x half>, <4 x half> addrspace(1)* %in
- %cvt = fpext <4 x half> %val to <4 x float>
- store <4 x float> %cvt, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v8f16_to_v8f32:
-define void @global_extload_v8f16_to_v8f32(<8 x float> addrspace(1)* %out, <8 x half> addrspace(1)* %in) #0 {
- %val = load <8 x half>, <8 x half> addrspace(1)* %in
- %cvt = fpext <8 x half> %val to <8 x float>
- store <8 x float> %cvt, <8 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v16f16_to_v16f32:
-define void @global_extload_v16f16_to_v16f32(<16 x float> addrspace(1)* %out, <16 x half> addrspace(1)* %in) #0 {
- %val = load <16 x half>, <16 x half> addrspace(1)* %in
- %cvt = fpext <16 x half> %val to <16 x float>
- store <16 x float> %cvt, <16 x float> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_f16_to_f64:
-; GCN: buffer_load_ushort [[LOAD:v[0-9]+]]
-; GCN: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], [[LOAD]]
-; GCN: v_cvt_f64_f32_e32 [[CVT1:v\[[0-9]+:[0-9]+\]]], [[CVT0]]
-; GCN: buffer_store_dwordx2 [[CVT1]]
-define void @global_extload_f16_to_f64(double addrspace(1)* %out, half addrspace(1)* %in) #0 {
- %val = load half, half addrspace(1)* %in
- %cvt = fpext half %val to double
- store double %cvt, double addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v2f16_to_v2f64:
-define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
- %val = load <2 x half>, <2 x half> addrspace(1)* %in
- %cvt = fpext <2 x half> %val to <2 x double>
- store <2 x double> %cvt, <2 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f64:
-define void @global_extload_v3f16_to_v3f64(<3 x double> addrspace(1)* %out, <3 x half> addrspace(1)* %in) #0 {
- %val = load <3 x half>, <3 x half> addrspace(1)* %in
- %cvt = fpext <3 x half> %val to <3 x double>
- store <3 x double> %cvt, <3 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v4f16_to_v4f64:
-define void @global_extload_v4f16_to_v4f64(<4 x double> addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
- %val = load <4 x half>, <4 x half> addrspace(1)* %in
- %cvt = fpext <4 x half> %val to <4 x double>
- store <4 x double> %cvt, <4 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v8f16_to_v8f64:
-define void @global_extload_v8f16_to_v8f64(<8 x double> addrspace(1)* %out, <8 x half> addrspace(1)* %in) #0 {
- %val = load <8 x half>, <8 x half> addrspace(1)* %in
- %cvt = fpext <8 x half> %val to <8 x double>
- store <8 x double> %cvt, <8 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_extload_v16f16_to_v16f64:
-define void @global_extload_v16f16_to_v16f64(<16 x double> addrspace(1)* %out, <16 x half> addrspace(1)* %in) #0 {
- %val = load <16 x half>, <16 x half> addrspace(1)* %in
- %cvt = fpext <16 x half> %val to <16 x double>
- store <16 x double> %cvt, <16 x double> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_truncstore_f32_to_f16:
-; GCN: buffer_load_dword [[LOAD:v[0-9]+]]
-; GCN: v_cvt_f16_f32_e32 [[CVT:v[0-9]+]], [[LOAD]]
-; GCN: buffer_store_short [[CVT]]
-define void @global_truncstore_f32_to_f16(half addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %val = load float, float addrspace(1)* %in
- %cvt = fptrunc float %val to half
- store half %cvt, half addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_truncstore_v2f32_to_v2f16:
-; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
-; GCN-DAG: v_cvt_f16_f32_e32 [[CVT0:v[0-9]+]], v[[LO]]
-; GCN-DAG: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], v[[HI]]
-; GCN-DAG: buffer_store_short [[CVT0]]
-; GCN-DAG: buffer_store_short [[CVT1]]
-; GCN: s_endpgm
-define void @global_truncstore_v2f32_to_v2f16(<2 x half> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 {
- %val = load <2 x float>, <2 x float> addrspace(1)* %in
- %cvt = fptrunc <2 x float> %val to <2 x half>
- store <2 x half> %cvt, <2 x half> addrspace(1)* %out
- ret void
-}
-
-; FIXME: Shouldn't do 4th conversion
-; GCN-LABEL: {{^}}global_truncstore_v3f32_to_v3f16:
-; GCN: buffer_load_dwordx4
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: buffer_store_short
-; GCN: buffer_store_dword
-; GCN: s_endpgm
-define void @global_truncstore_v3f32_to_v3f16(<3 x half> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 {
- %val = load <3 x float>, <3 x float> addrspace(1)* %in
- %cvt = fptrunc <3 x float> %val to <3 x half>
- store <3 x half> %cvt, <3 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_truncstore_v4f32_to_v4f16:
-; GCN: buffer_load_dwordx4
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: s_endpgm
-define void @global_truncstore_v4f32_to_v4f16(<4 x half> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
- %val = load <4 x float>, <4 x float> addrspace(1)* %in
- %cvt = fptrunc <4 x float> %val to <4 x half>
- store <4 x half> %cvt, <4 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_truncstore_v8f32_to_v8f16:
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: s_endpgm
-define void @global_truncstore_v8f32_to_v8f16(<8 x half> addrspace(1)* %out, <8 x float> addrspace(1)* %in) #0 {
- %val = load <8 x float>, <8 x float> addrspace(1)* %in
- %cvt = fptrunc <8 x float> %val to <8 x half>
- store <8 x half> %cvt, <8 x half> addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}global_truncstore_v16f32_to_v16f16:
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: buffer_load_dword
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: v_cvt_f16_f32_e32
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: buffer_store_short
-; GCN: s_endpgm
-define void @global_truncstore_v16f32_to_v16f16(<16 x half> addrspace(1)* %out, <16 x float> addrspace(1)* %in) #0 {
- %val = load <16 x float>, <16 x float> addrspace(1)* %in
- %cvt = fptrunc <16 x float> %val to <16 x half>
- store <16 x half> %cvt, <16 x half> addrspace(1)* %out
- ret void
-}
-
-; FIXME: Unsafe math should fold conversions away
-; GCN-LABEL: {{^}}fadd_f16:
-; SI-DAG: v_cvt_f32_f16_e32 v{{[0-9]+}},
-; SI-DAG: v_cvt_f32_f16_e32 v{{[0-9]+}},
-; SI-DAG: v_cvt_f32_f16_e32 v{{[0-9]+}},
-; SI-DAG: v_cvt_f32_f16_e32 v{{[0-9]+}},
-; SI: v_add_f32
-; GCN: s_endpgm
-define void @fadd_f16(half addrspace(1)* %out, half %a, half %b) #0 {
- %add = fadd half %a, %b
- store half %add, half addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}fadd_v2f16:
-; SI: v_add_f32
-; SI: v_add_f32
-; GCN: s_endpgm
-define void @fadd_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %a, <2 x half> %b) #0 {
- %add = fadd <2 x half> %a, %b
- store <2 x half> %add, <2 x half> addrspace(1)* %out, align 8
- ret void
-}
-
-; GCN-LABEL: {{^}}fadd_v4f16:
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; GCN: s_endpgm
-define void @fadd_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
- %b_ptr = getelementptr <4 x half>, <4 x half> addrspace(1)* %in, i32 1
- %a = load <4 x half>, <4 x half> addrspace(1)* %in, align 16
- %b = load <4 x half>, <4 x half> addrspace(1)* %b_ptr, align 16
- %result = fadd <4 x half> %a, %b
- store <4 x half> %result, <4 x half> addrspace(1)* %out, align 16
- ret void
-}
-
-; GCN-LABEL: {{^}}fadd_v8f16:
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; SI: v_add_f32
-; GCN: s_endpgm
-define void @fadd_v8f16(<8 x half> addrspace(1)* %out, <8 x half> %a, <8 x half> %b) #0 {
- %add = fadd <8 x half> %a, %b
- store <8 x half> %add, <8 x half> addrspace(1)* %out, align 32
- ret void
-}
-
-; GCN-LABEL: {{^}}fsub_f16:
-; GCN: v_subrev_f32_e32
-; GCN: s_endpgm
-define void @fsub_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 {
- %b_ptr = getelementptr half, half addrspace(1)* %in, i32 1
- %a = load half, half addrspace(1)* %in
- %b = load half, half addrspace(1)* %b_ptr
- %sub = fsub half %a, %b
- store half %sub, half addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}test_bitcast_from_half:
-; GCN: buffer_load_ushort [[TMP:v[0-9]+]]
-; GCN: buffer_store_short [[TMP]]
-define void @test_bitcast_from_half(half addrspace(1)* %in, i16 addrspace(1)* %out) #0 {
- %val = load half, half addrspace(1)* %in
- %val_int = bitcast half %val to i16
- store i16 %val_int, i16 addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}test_bitcast_to_half:
-; GCN: buffer_load_ushort [[TMP:v[0-9]+]]
-; GCN: buffer_store_short [[TMP]]
-define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in) #0 {
- %val = load i16, i16 addrspace(1)* %in
- %val_fp = bitcast i16 %val to half
- store half %val_fp, half addrspace(1)* %out
- ret void
-}
-
-attributes #0 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/hsa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/hsa.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/hsa.ll (original)
+++ llvm/trunk/test/CodeGen/R600/hsa.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
-
-; HSA: .section .hsa.version
-; HSA-NEXT: .ascii "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
-; HSA: {{^}}simple:
-; Make sure we are setting the ATC bit:
-; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
-; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
-
-define void @simple(i32 addrspace(1)* %out) {
-entry:
- store i32 0, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/i1-copy-implicit-def.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/i1-copy-implicit-def.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/i1-copy-implicit-def.ll (original)
+++ llvm/trunk/test/CodeGen/R600/i1-copy-implicit-def.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SILowerI1Copies was not handling IMPLICIT_DEF
-; SI-LABEL: {{^}}br_implicit_def:
-; SI: BB#0:
-; SI-NEXT: s_and_saveexec_b64
-; SI-NEXT: s_xor_b64
-; SI-NEXT: BB#1:
-define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 {
-bb:
- br i1 undef, label %bb1, label %bb2
-
-bb1:
- store volatile i32 123, i32 addrspace(1)* %out
- ret void
-
-bb2:
- ret void
-}
-
-attributes #0 = { nounwind }
Removed: llvm/trunk/test/CodeGen/R600/i1-copy-phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/i1-copy-phi.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/i1-copy-phi.ll (original)
+++ llvm/trunk/test/CodeGen/R600/i1-copy-phi.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}br_i1_phi:
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
-; SI: s_and_saveexec_b64
-; SI: s_xor_b64
-; SI: v_mov_b32_e32 [[REG]], -1{{$}}
-; SI: v_cmp_ne_i32_e32 vcc, 0, [[REG]]
-; SI: s_and_saveexec_b64
-; SI: s_xor_b64
-; SI: s_endpgm
-define void @br_i1_phi(i32 %arg, i1 %arg1) #0 {
-bb:
- br i1 %arg1, label %bb2, label %bb3
-
-bb2: ; preds = %bb
- br label %bb3
-
-bb3: ; preds = %bb2, %bb
- %tmp = phi i1 [ true, %bb2 ], [ false, %bb ]
- br i1 %tmp, label %bb4, label %bb6
-
-bb4: ; preds = %bb3
- %tmp5 = mul i32 undef, %arg
- br label %bb6
-
-bb6: ; preds = %bb4, %bb3
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll (original)
+++ llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll (removed)
@@ -1,11 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
- %1 = load i8, i8 addrspace(1)* %in
- %2 = uitofp i8 %1 to double
- %3 = fptrunc double %2 to float
- store float %3, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/icmp-select-sete-reverse-args.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/icmp-select-sete-reverse-args.ll (original)
+++ llvm/trunk/test/CodeGen/R600/icmp-select-sete-reverse-args.ll (removed)
@@ -1,18 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;Test that a select with reversed True/False values is correctly lowered
-;to a SETNE_INT. There should only be one SETNE_INT instruction.
-
-;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK-NOT: SETNE_INT
-
-define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-entry:
- %0 = load i32, i32 addrspace(1)* %in
- %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
- %1 = load i32, i32 addrspace(1)* %arrayidx1
- %cmp = icmp eq i32 %0, %1
- %value = select i1 %cmp, i32 0, i32 -1
- store i32 %value, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/icmp64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/icmp64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/icmp64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/icmp64.ll (removed)
@@ -1,93 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}test_i64_eq:
-; SI: v_cmp_eq_i64
-define void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp eq i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_ne:
-; SI: v_cmp_ne_i64
-define void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp ne i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_slt:
-; SI: v_cmp_lt_i64
-define void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp slt i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_ult:
-; SI: v_cmp_lt_u64
-define void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp ult i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_sle:
-; SI: v_cmp_le_i64
-define void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp sle i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_ule:
-; SI: v_cmp_le_u64
-define void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp ule i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_sgt:
-; SI: v_cmp_gt_i64
-define void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp sgt i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_ugt:
-; SI: v_cmp_gt_u64
-define void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp ugt i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_sge:
-; SI: v_cmp_ge_i64
-define void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp sge i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_i64_uge:
-; SI: v_cmp_ge_u64
-define void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
- %cmp = icmp uge i64 %a, %b
- %result = sext i1 %cmp to i32
- store i32 %result, i32 addrspace(1)* %out, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/imm.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/imm.ll (original)
+++ llvm/trunk/test/CodeGen/R600/imm.ll (removed)
@@ -1,617 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=CHECK %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CHECK %s
-
-; Use a 64-bit value with lo bits that can be represented as an inline constant
-; CHECK-LABEL: {{^}}i64_imm_inline_lo:
-; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5
-; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]:
-define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
-entry:
- store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
- ret void
-}
-
-; Use a 64-bit value with hi bits that can be represented as an inline constant
-; CHECK-LABEL: {{^}}i64_imm_inline_hi:
-; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5
-; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
-; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
-define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
-entry:
- store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64:
-; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000
-; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) {
- store i64 -9223372036854775808, i64 addrspace(1) *%out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) {
- store i32 -2147483648, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
- store float 0.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
-; CHECK: buffer_store_dword [[REG]]
-define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
- store float -0.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
- store float 0.5, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
- store float -0.5, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
- store float 1.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
- store float -1.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
- store float 2.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
- store float -2.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
- store float 4.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
- store float -4.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_literal_imm_f32:
-; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
-; CHECK: buffer_store_dword [[REG]]
-define void @store_literal_imm_f32(float addrspace(1)* %out) {
- store float 4096.0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0.5
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, -0.5
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 1.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, -1.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 2.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, -2.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 4.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, -4.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}commute_add_inline_imm_0.5_f32:
-; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
-; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %x = load float, float addrspace(1)* %in
- %y = fadd float %x, 0.5
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}commute_add_literal_f32:
-; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
-; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
- %x = load float, float addrspace(1)* %in
- %y = fadd float %x, 1024.0
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_1_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0x36a0000000000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_2_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0x36b0000000000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_16_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0x36e0000000000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0xffffffffe0000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0xffffffffc0000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0xfffffffe00000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_63_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0x36ff800000000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_64_f32:
-; CHECK: s_load_dword [[VAL:s[0-9]+]]
-; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
-; CHECK: buffer_store_dword [[REG]]
-define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
- %y = fadd float %x, 0x3700000000000000
- store float %y, float addrspace(1)* %out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0.5
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, -0.5
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 1.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, -1.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 2.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, -2.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 4.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, -4.0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}add_inline_imm_1_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0x0000000000000001
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_2_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0x0000000000000002
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_16_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0x0000000000000010
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0xffffffffffffffff
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0xfffffffffffffffe
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0xfffffffffffffff0
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_63_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0x000000000000003F
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}add_inline_imm_64_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]]
-; CHECK: buffer_store_dwordx2 [[REG]]
-define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
- %y = fadd double %x, 0x0000000000000040
- store double %y, double addrspace(1)* %out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64:
-; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
-; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
- store double 0.0, double addrspace(1)* %out
- ret void
-}
-
-
-; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64:
-; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000
-; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) {
- store double -0.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_0.5_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) {
- store double 0.5, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) {
- store double -0.5, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_1.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) {
- store double 1.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) {
- store double -1.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_2.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) {
- store double 2.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) {
- store double -2.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_4.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) {
- store double 4.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f64:
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) {
- store double -4.0, double addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}store_literal_imm_f64:
-; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x40b00000
-; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}}
-; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
-; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
-; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
-define void @store_literal_imm_f64(double addrspace(1)* %out) {
- store double 4096.0, double addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/indirect-addressing-si.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/indirect-addressing-si.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/indirect-addressing-si.ll (original)
+++ llvm/trunk/test/CodeGen/R600/indirect-addressing-si.ll (removed)
@@ -1,121 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; Tests for indirect addressing on SI, which is implemented using dynamic
-; indexing of vectors.
-
-; CHECK-LABEL: {{^}}extract_w_offset:
-; CHECK: s_mov_b32 m0
-; CHECK-NEXT: v_movrels_b32_e32
-define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
-entry:
- %0 = add i32 %in, 1
- %1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0
- store float %1, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}extract_wo_offset:
-; CHECK: s_mov_b32 m0
-; CHECK-NEXT: v_movrels_b32_e32
-define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
-entry:
- %0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}extract_neg_offset_sgpr:
-; The offset depends on the register that holds the first element of the vector.
-; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
-; CHECK: v_movrels_b32_e32 v{{[0-9]}}, v0
-define void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) {
-entry:
- %index = add i32 %offset, -512
- %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
- store i32 %value, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}extract_neg_offset_vgpr:
-; The offset depends on the register that holds the first element of the vector.
-; CHECK: v_readfirstlane_b32
-; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
-; CHECK-NEXT: v_movrels_b32_e32 v{{[0-9]}}, v0
-; CHECK: s_cbranch_execnz
-define void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) {
-entry:
- %id = call i32 @llvm.r600.read.tidig.x() #1
- %index = add i32 %id, -512
- %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
- store i32 %value, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}insert_w_offset:
-; CHECK: s_mov_b32 m0
-; CHECK-NEXT: v_movreld_b32_e32
-define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
-entry:
- %0 = add i32 %in, 1
- %1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
- %2 = extractelement <4 x float> %1, i32 2
- store float %2, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}insert_wo_offset:
-; CHECK: s_mov_b32 m0
-; CHECK-NEXT: v_movreld_b32_e32
-define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
-entry:
- %0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
- %1 = extractelement <4 x float> %0, i32 2
- store float %1, float addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}insert_neg_offset_sgpr:
-; The offset depends on the register that holds the first element of the vector.
-; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
-; CHECK: v_movreld_b32_e32 v0, v{{[0-9]}}
-define void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out, i32 %offset) {
-entry:
- %index = add i32 %offset, -512
- %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
- store <4 x i32> %value, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}insert_neg_offset_vgpr:
-; The offset depends on the register that holds the first element of the vector.
-; CHECK: v_readfirstlane_b32
-; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
-; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
-; CHECK: s_cbranch_execnz
-define void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
-entry:
- %id = call i32 @llvm.r600.read.tidig.x() #1
- %index = add i32 %id, -512
- %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
- store <4 x i32> %value, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; CHECK-LABEL: {{^}}insert_neg_inline_offset_vgpr:
-; The offset depends on the register that holds the first element of the vector.
-; CHECK: v_readfirstlane_b32
-; CHECK: s_add_i32 m0, m0, -{{[0-9]+}}
-; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
-; CHECK: s_cbranch_execnz
-define void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
-entry:
- %id = call i32 @llvm.r600.read.tidig.x() #1
- %index = add i32 %id, -16
- %value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
- store <4 x i32> %value, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-declare i32 @llvm.r600.read.tidig.x() #1
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/indirect-private-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/indirect-private-64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/indirect-private-64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/indirect-private-64.ll (removed)
@@ -1,91 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
-
-
-declare void @llvm.AMDGPU.barrier.local() noduplicate nounwind
-
-; SI-LABEL: {{^}}private_access_f64_alloca:
-
-; SI-ALLOCA: buffer_store_dwordx2
-; SI-ALLOCA: buffer_load_dwordx2
-
-; SI-PROMOTE: ds_write_b64
-; SI-PROMOTE: ds_read_b64
-define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind {
- %val = load double, double addrspace(1)* %in, align 8
- %array = alloca double, i32 16, align 8
- %ptr = getelementptr double, double* %array, i32 %b
- store double %val, double* %ptr, align 8
- call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
- %result = load double, double* %ptr, align 8
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}private_access_v2f64_alloca:
-
-; SI-ALLOCA: buffer_store_dwordx4
-; SI-ALLOCA: buffer_load_dwordx4
-
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
- %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
- %array = alloca <2 x double>, i32 16, align 16
- %ptr = getelementptr <2 x double>, <2 x double>* %array, i32 %b
- store <2 x double> %val, <2 x double>* %ptr, align 16
- call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
- %result = load <2 x double>, <2 x double>* %ptr, align 16
- store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}private_access_i64_alloca:
-
-; SI-ALLOCA: buffer_store_dwordx2
-; SI-ALLOCA: buffer_load_dwordx2
-
-; SI-PROMOTE: ds_write_b64
-; SI-PROMOTE: ds_read_b64
-define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind {
- %val = load i64, i64 addrspace(1)* %in, align 8
- %array = alloca i64, i32 16, align 8
- %ptr = getelementptr i64, i64* %array, i32 %b
- store i64 %val, i64* %ptr, align 8
- call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
- %result = load i64, i64* %ptr, align 8
- store i64 %result, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}private_access_v2i64_alloca:
-
-; SI-ALLOCA: buffer_store_dwordx4
-; SI-ALLOCA: buffer_load_dwordx4
-
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_write_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-; SI-PROMOTE: ds_read_b32
-define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
- %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
- %array = alloca <2 x i64>, i32 16, align 16
- %ptr = getelementptr <2 x i64>, <2 x i64>* %array, i32 %b
- store <2 x i64> %val, <2 x i64>* %ptr, align 16
- call void @llvm.AMDGPU.barrier.local() noduplicate nounwind
- %result = load <2 x i64>, <2 x i64>* %ptr, align 16
- store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/infinite-loop-evergreen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/infinite-loop-evergreen.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/infinite-loop-evergreen.ll (original)
+++ llvm/trunk/test/CodeGen/R600/infinite-loop-evergreen.ll (removed)
@@ -1,10 +0,0 @@
-; XFAIL: *
-; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s
-
-define void @inf_loop_irreducible_cfg() nounwind {
-entry:
- br label %block
-
-block:
- br label %block
-}
Removed: llvm/trunk/test/CodeGen/R600/infinite-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/infinite-loop.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/infinite-loop.ll (original)
+++ llvm/trunk/test/CodeGen/R600/infinite-loop.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}infinite_loop:
-; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7
-; SI: BB0_1:
-; SI: buffer_store_dword [[REG]]
-; SI: s_waitcnt vmcnt(0) expcnt(0)
-; SI: s_branch BB0_1
-define void @infinite_loop(i32 addrspace(1)* %out) {
-entry:
- br label %for.body
-
-for.body: ; preds = %entry, %for.body
- store i32 999, i32 addrspace(1)* %out, align 4
- br label %for.body
-}
-
Removed: llvm/trunk/test/CodeGen/R600/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/inline-asm.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/R600/inline-asm.ll (removed)
@@ -1,12 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
-
-; CHECK: {{^}}inline_asm:
-; CHECK: s_endpgm
-; CHECK: s_endpgm
-define void @inline_asm(i32 addrspace(1)* %out) {
-entry:
- store i32 5, i32 addrspace(1)* %out
- call void asm sideeffect "s_endpgm", ""()
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/inline-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/inline-calls.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/inline-calls.ll (original)
+++ llvm/trunk/test/CodeGen/R600/inline-calls.ll (removed)
@@ -1,25 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s
-
-; CHECK-NOT: {{^}}func:
-define internal fastcc i32 @func(i32 %a) {
-entry:
- %tmp0 = add i32 %a, 1
- ret i32 %tmp0
-}
-
-; CHECK: {{^}}kernel:
-define void @kernel(i32 addrspace(1)* %out) {
-entry:
- %tmp0 = call i32 @func(i32 1)
- store i32 %tmp0, i32 addrspace(1)* %out
- ret void
-}
-
-; CHECK: {{^}}kernel2:
-define void @kernel2(i32 addrspace(1)* %out) {
-entry:
- call void @kernel(i32 addrspace(1)* %out)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/input-mods.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/input-mods.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/input-mods.ll (original)
+++ llvm/trunk/test/CodeGen/R600/input-mods.ll (removed)
@@ -1,26 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG
-;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM
-
-;EG-LABEL: {{^}}test:
-;EG: EXP_IEEE *
-;CM-LABEL: {{^}}test:
-;CM: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X|
-;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X|
-;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X|
-;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X|
-
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = call float @llvm.fabs.f32(float %r0)
- %r2 = fsub float -0.000000e+00, %r1
- %r3 = call float @llvm.exp2.f32(float %r2)
- %vec = insertelement <4 x float> undef, float %r3, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare float @llvm.exp2.f32(float) readnone
-declare float @llvm.fabs.f32(float) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
Removed: llvm/trunk/test/CodeGen/R600/insert_subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/insert_subreg.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/insert_subreg.ll (original)
+++ llvm/trunk/test/CodeGen/R600/insert_subreg.ll (removed)
@@ -1,16 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s
-
-; Test that INSERT_SUBREG instructions don't have non-register operands after
-; instruction selection.
-
-; Make sure this doesn't crash
-; CHECK-LABEL: test:
-define void @test(i64 addrspace(1)* %out) {
-entry:
- %tmp0 = alloca [16 x i32]
- %tmp1 = ptrtoint [16 x i32]* %tmp0 to i32
- %tmp2 = sext i32 %tmp1 to i64
- store i64 %tmp2, i64 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll (original)
+++ llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll (removed)
@@ -1,252 +0,0 @@
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
-
-; FIXME: Broken on evergreen
-; FIXME: For some reason the 8 and 16 vectors are being stored as
-; individual elements instead of 128-bit stores.
-
-
-; FIXME: Why is the constant moved into the intermediate register and
-; not just directly into the vector component?
-
-; SI-LABEL: {{^}}insertelement_v4f32_0:
-; s_load_dwordx4 s{{[}}[[LOW_REG:[0-9]+]]:
-; v_mov_b32_e32
-; v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 5.000000e+00
-; v_mov_b32_e32 v[[LOW_REG]], [[CONSTREG]]
-; buffer_store_dwordx4 v{{[}}[[LOW_REG]]:
-define void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
- %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0
- store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}insertelement_v4f32_1:
-define void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
- %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1
- store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}insertelement_v4f32_2:
-define void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
- %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2
- store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}insertelement_v4f32_3:
-define void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind {
- %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3
- store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}insertelement_v4i32_0:
-define void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind {
- %vecins = insertelement <4 x i32> %a, i32 999, i32 0
- store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2f32:
-; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
-; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
-; SI: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]:
-define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b
- store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v4f32:
-; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
-; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
-; SI: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]:
-define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind {
- %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b
- store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v8f32:
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind {
- %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
- store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v16f32:
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind {
- %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b
- store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2i32:
-; SI: buffer_store_dwordx2
-define void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x i32> %a, i32 5, i32 %b
- store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v4i32:
-; SI: buffer_store_dwordx4
-define void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b) nounwind {
- %vecins = insertelement <4 x i32> %a, i32 5, i32 %b
- store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v8i32:
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind {
- %vecins = insertelement <8 x i32> %a, i32 5, i32 %b
- store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v16i32:
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind {
- %vecins = insertelement <16 x i32> %a, i32 5, i32 %b
- store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64
- ret void
-}
-
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2i16:
-; FIXMESI: buffer_store_dwordx2
-define void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x i16> %a, i16 5, i32 %b
- store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v4i16:
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, i32 %b) nounwind {
- %vecins = insertelement <4 x i16> %a, i16 5, i32 %b
- store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out, align 16
- ret void
-}
-
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2i8:
-; FIXMESI: BUFFER_STORE_USHORT
-define void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x i8> %a, i8 5, i32 %b
- store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v4i8:
-; FIXMESI: buffer_store_dword
-define void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind {
- %vecins = insertelement <4 x i8> %a, i8 5, i32 %b
- store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v8i8:
-; FIXMESI: buffer_store_dwordx2
-define void @dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> %a, i32 %b) nounwind {
- %vecins = insertelement <8 x i8> %a, i8 5, i32 %b
- store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v16i8:
-; FIXMESI: buffer_store_dwordx4
-define void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind {
- %vecins = insertelement <16 x i8> %a, i8 5, i32 %b
- store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
- ret void
-}
-
-; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that
-; the compiler doesn't crash.
-; SI-LABEL: {{^}}insert_split_bb:
-define void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
-entry:
- %0 = insertelement <2 x i32> undef, i32 %a, i32 0
- %1 = icmp eq i32 %a, 0
- br i1 %1, label %if, label %else
-
-if:
- %2 = load i32, i32 addrspace(1)* %in
- %3 = insertelement <2 x i32> %0, i32 %2, i32 1
- br label %endif
-
-else:
- %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1
- %5 = load i32, i32 addrspace(1)* %4
- %6 = insertelement <2 x i32> %0, i32 %5, i32 1
- br label %endif
-
-endif:
- %7 = phi <2 x i32> [%3, %if], [%6, %else]
- store <2 x i32> %7, <2 x i32> addrspace(1)* %out
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2f64:
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x double> %a, double 8.0, i32 %b
- store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v2i64:
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind {
- %vecins = insertelement <2 x i64> %a, i64 5, i32 %b
- store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v4f64:
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind {
- %vecins = insertelement <4 x double> %a, double 8.0, i32 %b
- store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16
- ret void
-}
-
-; SI-LABEL: {{^}}dynamic_insertelement_v8f64:
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
-define void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) nounwind {
- %vecins = insertelement <8 x double> %a, double 8.0, i32 %b
- store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/jump-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/jump-address.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/jump-address.ll (original)
+++ llvm/trunk/test/CodeGen/R600/jump-address.ll (removed)
@@ -1,52 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: JUMP @6
-; CHECK: EXPORT
-; CHECK-NOT: EXPORT
-
-define void @main() #0 {
-main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %1 = extractelement <4 x float> %0, i32 0
- %2 = bitcast float %1 to i32
- %3 = icmp eq i32 %2, 0
- %4 = sext i1 %3 to i32
- %5 = bitcast i32 %4 to float
- %6 = bitcast float %5 to i32
- %7 = icmp ne i32 %6, 0
- br i1 %7, label %ENDIF, label %ELSE
-
-ELSE: ; preds = %main_body
- %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %9 = extractelement <4 x float> %8, i32 0
- %10 = bitcast float %9 to i32
- %11 = icmp eq i32 %10, 1
- %12 = sext i1 %11 to i32
- %13 = bitcast i32 %12 to float
- %14 = bitcast float %13 to i32
- %15 = icmp ne i32 %14, 0
- br i1 %15, label %IF13, label %ENDIF
-
-ENDIF: ; preds = %IF13, %ELSE, %main_body
- %temp.0 = phi float [ 0xFFF8000000000000, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
- %temp2.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %temp3.0 = phi float [ 5.000000e-01, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %16 = insertelement <4 x float> undef, float %temp.0, i32 0
- %17 = insertelement <4 x float> %16, float %temp1.0, i32 1
- %18 = insertelement <4 x float> %17, float %temp2.0, i32 2
- %19 = insertelement <4 x float> %18, float %temp3.0, i32 3
- call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
- ret void
-
-IF13: ; preds = %ELSE
- %20 = load <4 x float>, <4 x float> addrspace(8)* null
- %21 = extractelement <4 x float> %20, i32 0
- %22 = fsub float -0.000000e+00, %21
- %23 = fadd float 0xFFF8000000000000, %22
- br label %ENDIF
-}
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
Removed: llvm/trunk/test/CodeGen/R600/kcache-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/kcache-fold.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/kcache-fold.ll (original)
+++ llvm/trunk/test/CodeGen/R600/kcache-fold.ll (removed)
@@ -1,100 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}main1:
-; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}}
-define void @main1() {
-main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = extractelement <4 x float> %0, i32 0
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %3 = extractelement <4 x float> %2, i32 0
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %5 = extractelement <4 x float> %4, i32 0
- %6 = fcmp ogt float %1, 0.000000e+00
- %7 = select i1 %6, float %3, float %5
- %8 = load <4 x float>, <4 x float> addrspace(8)* null
- %9 = extractelement <4 x float> %8, i32 1
- %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %11 = extractelement <4 x float> %10, i32 1
- %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %13 = extractelement <4 x float> %12, i32 1
- %14 = fcmp ogt float %9, 0.000000e+00
- %15 = select i1 %14, float %11, float %13
- %16 = load <4 x float>, <4 x float> addrspace(8)* null
- %17 = extractelement <4 x float> %16, i32 2
- %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %19 = extractelement <4 x float> %18, i32 2
- %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %21 = extractelement <4 x float> %20, i32 2
- %22 = fcmp ogt float %17, 0.000000e+00
- %23 = select i1 %22, float %19, float %21
- %24 = load <4 x float>, <4 x float> addrspace(8)* null
- %25 = extractelement <4 x float> %24, i32 3
- %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %27 = extractelement <4 x float> %26, i32 3
- %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %29 = extractelement <4 x float> %28, i32 3
- %30 = fcmp ogt float %25, 0.000000e+00
- %31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
- %36 = insertelement <4 x float> undef, float %32, i32 0
- %37 = insertelement <4 x float> %36, float %33, i32 1
- %38 = insertelement <4 x float> %37, float %34, i32 2
- %39 = insertelement <4 x float> %38, float %35, i32 3
- call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0)
- ret void
-}
-
-; CHECK: {{^}}main2:
-; CHECK-NOT: MOV
-define void @main2() {
-main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* null
- %1 = extractelement <4 x float> %0, i32 0
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %3 = extractelement <4 x float> %2, i32 0
- %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %5 = extractelement <4 x float> %4, i32 1
- %6 = fcmp ogt float %1, 0.000000e+00
- %7 = select i1 %6, float %3, float %5
- %8 = load <4 x float>, <4 x float> addrspace(8)* null
- %9 = extractelement <4 x float> %8, i32 1
- %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %11 = extractelement <4 x float> %10, i32 0
- %12 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %13 = extractelement <4 x float> %12, i32 1
- %14 = fcmp ogt float %9, 0.000000e+00
- %15 = select i1 %14, float %11, float %13
- %16 = load <4 x float>, <4 x float> addrspace(8)* null
- %17 = extractelement <4 x float> %16, i32 2
- %18 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %19 = extractelement <4 x float> %18, i32 3
- %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %21 = extractelement <4 x float> %20, i32 2
- %22 = fcmp ogt float %17, 0.000000e+00
- %23 = select i1 %22, float %19, float %21
- %24 = load <4 x float>, <4 x float> addrspace(8)* null
- %25 = extractelement <4 x float> %24, i32 3
- %26 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %27 = extractelement <4 x float> %26, i32 3
- %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
- %29 = extractelement <4 x float> %28, i32 2
- %30 = fcmp ogt float %25, 0.000000e+00
- %31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
- %36 = insertelement <4 x float> undef, float %32, i32 0
- %37 = insertelement <4 x float> %36, float %33, i32 1
- %38 = insertelement <4 x float> %37, float %34, i32 2
- %39 = insertelement <4 x float> %38, float %35, i32 3
- call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0)
- ret void
-}
-
-declare float @llvm.AMDIL.clamp.(float, float, float) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Removed: llvm/trunk/test/CodeGen/R600/kernel-args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/kernel-args.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/kernel-args.ll (original)
+++ llvm/trunk/test/CodeGen/R600/kernel-args.ll (removed)
@@ -1,473 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
-
-; FUNC-LABEL: {{^}}i8_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; GCN: buffer_load_ubyte
-
-define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
-entry:
- %0 = zext i8 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i8_zext_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-
-define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
-entry:
- %0 = zext i8 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i8_sext_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-
-define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
-entry:
- %0 = sext i8 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i16_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; GCN: buffer_load_ushort
-
-define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
-entry:
- %0 = zext i16 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i16_zext_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-
-define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
-entry:
- %0 = zext i16 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i16_sext_arg:
-; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-
-define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
-entry:
- %0 = sext i16 %in to i32
- store i32 %0, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}i32_arg:
-; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
-entry:
- store i32 %in, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}f32_arg:
-; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z
-; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
-; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
-define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
-entry:
- store float %in, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v2i8_arg:
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
-entry:
- store <2 x i8> %in, <2 x i8> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v2i16_arg:
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; GCN-DAG: buffer_load_ushort
-; GCN-DAG: buffer_load_ushort
-define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
-entry:
- store <2 x i16> %in, <2 x i16> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v2i32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
-; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
-; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
-define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
-entry:
- store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v2f32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
-; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
-; VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c
-define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
-entry:
- store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v3i8_arg:
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41
-; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42
-define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
-entry:
- store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v3i16_arg:
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
-; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48
-define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
-entry:
- store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
- ret void
-}
-; FUNC-LABEL: {{^}}v3i32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
-define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
-entry:
- store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v3f32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
-define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
-entry:
- store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v4i8_arg:
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
-entry:
- store <4 x i8> %in, <4 x i8> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v4i16_arg:
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
-entry:
- store <4 x i16> %in, <4 x i16> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v4i32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
-; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
-define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
-entry:
- store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v4f32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
-; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
-; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
-define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
-entry:
- store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v8i8_arg:
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
-entry:
- store <8 x i8> %in, <8 x i8> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v8i16_arg:
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
-entry:
- store <8 x i16> %in, <8 x i16> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v8i32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
-; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
-; VI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x44
-define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
-entry:
- store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v8f32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
-; SI: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
-define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
-entry:
- store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v16i8_arg:
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; EG: VTX_READ_8
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
-entry:
- store <16 x i8> %in, <16 x i8> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v16i16_arg:
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; EG: VTX_READ_16
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
-entry:
- store <16 x i16> %in, <16 x i16> addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}v16i32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
-; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
-; VI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
-define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
-entry:
- store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v16f32_arg:
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
-; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
-; SI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
-; VI: s_load_dwordx16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
-define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
-entry:
- store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}kernel_arg_i64:
-; GCN: s_load_dwordx2
-; GCN: s_load_dwordx2
-; GCN: buffer_store_dwordx2
-define void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {
- store i64 %a, i64 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}f64_kernel_arg:
-; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9
-; SI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb
-; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x24
-; VI-DAG: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[0:1], 0x2c
-; GCN: buffer_store_dwordx2
-define void @f64_kernel_arg(double addrspace(1)* %out, double %in) {
-entry:
- store double %in, double addrspace(1)* %out
- ret void
-}
-
-; XFUNC-LABEL: {{^}}kernel_arg_v1i64:
-; XGCN: s_load_dwordx2
-; XGCN: s_load_dwordx2
-; XGCN: buffer_store_dwordx2
-; define void @kernel_arg_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a) nounwind {
-; store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8
-; ret void
-; }
Removed: llvm/trunk/test/CodeGen/R600/large-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/large-alloca.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/large-alloca.ll (original)
+++ llvm/trunk/test/CodeGen/R600/large-alloca.ll (removed)
@@ -1,15 +0,0 @@
-; XFAIL: *
-; REQUIRES: asserts
-; RUN: llc -march=amdgcn -mcpu=SI < %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s
-
-define void @large_alloca(i32 addrspace(1)* %out, i32 %x, i32 %y) nounwind {
- %large = alloca [8192 x i32], align 4
- %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
- store i32 %x, i32* %gep
- %gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
- %0 = load i32, i32* %gep1
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/large-constant-initializer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/large-constant-initializer.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/large-constant-initializer.ll (original)
+++ llvm/trunk/test/CodeGen/R600/large-constant-initializer.ll (removed)
@@ -1,19 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s
-; CHECK: s_endpgm
-
- at gv = external unnamed_addr addrspace(2) constant [239 x i32], align 4
-
-define void @opencv_cvtfloat_crash(i32 addrspace(1)* %out, i32 %x) nounwind {
- %val = load i32, i32 addrspace(2)* getelementptr ([239 x i32], [239 x i32] addrspace(2)* @gv, i64 0, i64 239), align 4
- %mul12 = mul nsw i32 %val, 7
- br i1 undef, label %exit, label %bb
-
-bb:
- %cmp = icmp slt i32 %x, 0
- br label %exit
-
-exit:
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/lds-initializer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lds-initializer.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lds-initializer.ll (original)
+++ llvm/trunk/test/CodeGen/R600/lds-initializer.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s
-; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
-
-; CHECK: error: unsupported initializer for address space in load_init_lds_global
-
- at lds = addrspace(3) global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8]
-
-define void @load_init_lds_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [8 x i32], [8 x i32] addrspace(3)* @lds, i32 0, i32 10
- %ld = load i32, i32 addrspace(3)* %gep
- store i32 %ld, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/lds-oqap-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lds-oqap-crash.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lds-oqap-crash.ll (original)
+++ llvm/trunk/test/CodeGen/R600/lds-oqap-crash.ll (removed)
@@ -1,28 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s
-
-; The test is for a bug in R600EmitClauseMarkers.cpp where this pass
-; was searching for a use of the OQAP register in order to determine
-; if an LDS instruction could fit in the current clause, but never finding
-; one. This created an infinite loop and hung the compiler.
-;
-; The LDS instruction should not have been defining OQAP in the first place,
-; because the LDS instructions are pseudo instructions and the OQAP
-; reads and writes are bundled together in the same instruction.
-
-; CHECK: {{^}}lds_crash:
-define void @lds_crash(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %a, i32 %b, i32 %c) {
-entry:
- %0 = load i32, i32 addrspace(3)* %in
- ; This block needs to be > 115 ISA instructions to hit the bug,
- ; so we'll use udiv instructions.
- %div0 = udiv i32 %0, %b
- %div1 = udiv i32 %div0, %a
- %div2 = udiv i32 %div1, 11
- %div3 = udiv i32 %div2, %a
- %div4 = udiv i32 %div3, %b
- %div5 = udiv i32 %div4, %c
- %div6 = udiv i32 %div5, %div0
- %div7 = udiv i32 %div6, %div1
- store i32 %div7, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/lds-output-queue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lds-output-queue.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lds-output-queue.ll (original)
+++ llvm/trunk/test/CodeGen/R600/lds-output-queue.ll (removed)
@@ -1,99 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s
-;
-; This test checks that the lds input queue will is empty at the end of
-; the ALU clause.
-
-; CHECK-LABEL: {{^}}lds_input_queue:
-; CHECK: LDS_READ_RET * OQAP
-; CHECK-NOT: ALU clause
-; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
-
- at local_mem = internal unnamed_addr addrspace(3) global [2 x i32] undef, align 4
-
-define void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %index) {
-entry:
- %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
- %1 = load i32, i32 addrspace(3)* %0
- call void @llvm.AMDGPU.barrier.local()
-
- ; This will start a new clause for the vertex fetch
- %2 = load i32, i32 addrspace(1)* %in
- %3 = add i32 %1, %2
- store i32 %3, i32 addrspace(1)* %out
- ret void
-}
-
-declare void @llvm.AMDGPU.barrier.local()
-
-; The machine scheduler does not do proper alias analysis and assumes that
-; loads from global values (Note that a global value is different that a
-; value from global memory. A global value is a value that is declared
-; outside of a function, it can reside in any address space) alias with
-; all other loads.
-;
-; This is a problem for scheduling the reads from the local data share (lds).
-; These reads are implemented using two instructions. The first copies the
-; data from lds into the lds output queue, and the second moves the data from
-; the input queue into main memory. These two instructions don't have to be
-; scheduled one after the other, but they do need to be scheduled in the same
-; clause. The aliasing problem mentioned above causes problems when there is a
-; load from global memory which immediately follows a load from a global value that
-; has been declared in the local memory space:
-;
-; %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
-; %1 = load i32, i32 addrspace(3)* %0
-; %2 = load i32, i32 addrspace(1)* %in
-;
-; The instruction selection phase will generate ISA that looks like this:
-; %OQAP = LDS_READ_RET
-; %vreg0 = MOV %OQAP
-; %vreg1 = VTX_READ_32
-; %vreg2 = ADD_INT %vreg1, %vreg0
-;
-; The bottom scheduler will schedule the two ALU instructions first:
-;
-; UNSCHEDULED:
-; %OQAP = LDS_READ_RET
-; %vreg1 = VTX_READ_32
-;
-; SCHEDULED:
-;
-; vreg0 = MOV %OQAP
-; vreg2 = ADD_INT %vreg1, %vreg2
-;
-; The lack of proper aliasing results in the local memory read (LDS_READ_RET)
-; to consider the global memory read (VTX_READ_32) has a chain dependency, so
-; the global memory read will always be scheduled first. This will give us a
-; final program which looks like this:
-;
-; Alu clause:
-; %OQAP = LDS_READ_RET
-; VTX clause:
-; %vreg1 = VTX_READ_32
-; Alu clause:
-; vreg0 = MOV %OQAP
-; vreg2 = ADD_INT %vreg1, %vreg2
-;
-; This is an illegal program because the OQAP def and use know occur in
-; different ALU clauses.
-;
-; This test checks this scenario and makes sure it doesn't result in an
-; illegal program. For now, we have fixed this issue by merging the
-; LDS_READ_RET and MOV together during instruction selection and then
-; expanding them after scheduling. Once the scheduler has better alias
-; analysis, we should be able to keep these instructions sparate before
-; scheduling.
-;
-; CHECK-LABEL: {{^}}local_global_alias:
-; CHECK: LDS_READ_RET
-; CHECK-NOT: ALU clause
-; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
-define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-entry:
- %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
- %1 = load i32, i32 addrspace(3)* %0
- %2 = load i32, i32 addrspace(1)* %in
- %3 = add i32 %2, %1
- store i32 %3, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/lds-size.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lds-size.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lds-size.ll (original)
+++ llvm/trunk/test/CodeGen/R600/lds-size.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; This test makes sure we do not double count global values when they are
-; used in different basic blocks.
-
-; CHECK: .long 166120
-; CHECK-NEXT: .long 1
-; CHECK-LABEL: {{^}}test:
- at lds = internal unnamed_addr addrspace(3) global i32 undef, align 4
-
-define void @test(i32 addrspace(1)* %out, i32 %cond) {
-entry:
- %0 = icmp eq i32 %cond, 0
- br i1 %0, label %if, label %else
-
-if:
- store i32 1, i32 addrspace(3)* @lds
- br label %endif
-
-else:
- store i32 2, i32 addrspace(3)* @lds
- br label %endif
-
-endif:
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/lds-zero-initializer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lds-zero-initializer.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lds-zero-initializer.ll (original)
+++ llvm/trunk/test/CodeGen/R600/lds-zero-initializer.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s
-; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s
-
-; CHECK: error: unsupported initializer for address space in load_zeroinit_lds_global
-
- at lds = addrspace(3) global [256 x i32] zeroinitializer
-
-define void @load_zeroinit_lds_global(i32 addrspace(1)* %out, i1 %p) {
- %gep = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds, i32 0, i32 10
- %ld = load i32, i32 addrspace(3)* %gep
- store i32 %ld, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/R600/legalizedag-bug-expand-setcc.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; This tests a bug where LegalizeDAG was not checking the target's
-; BooleanContents value and always using one for true, when expanding
-; setcc to select_cc.
-;
-; This bug caused the icmp IR instruction to be expanded to two machine
-; instructions, when only one is needed.
-;
-
-; CHECK: {{^}}setcc_expand:
-; CHECK: SET
-; CHECK-NOT: CND
-define void @setcc_expand(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = icmp eq i32 %in, 5
- br i1 %0, label %IF, label %ENDIF
-IF:
- %1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
- store i32 0, i32 addrspace(1)* %1
- br label %ENDIF
-
-ENDIF:
- store i32 0, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/lit.local.cfg?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/lit.local.cfg (original)
+++ llvm/trunk/test/CodeGen/R600/lit.local.cfg (removed)
@@ -1,2 +0,0 @@
-if not 'R600' in config.root.targets:
- config.unsupported = True
Removed: llvm/trunk/test/CodeGen/R600/literals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/literals.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/literals.ll (original)
+++ llvm/trunk/test/CodeGen/R600/literals.ll (removed)
@@ -1,64 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; Test using an integer literal constant.
-; Generated ASM should be:
-; ADD_INT KC0[2].Z literal.x, 5
-; or
-; ADD_INT literal.x KC0[2].Z, 5
-
-; CHECK: {{^}}i32_literal:
-; CHECK: ADD_INT {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
-; CHECK-NEXT: LSHR
-; CHECK-NEXT: 5
-define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
-entry:
- %0 = add i32 5, %in
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
-; Test using a float literal constant.
-; Generated ASM should be:
-; ADD KC0[2].Z literal.x, 5.0
-; or
-; ADD literal.x KC0[2].Z, 5.0
-
-; CHECK: {{^}}float_literal:
-; CHECK: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
-; CHECK-NEXT: LSHR
-; CHECK-NEXT: 1084227584(5.0
-define void @float_literal(float addrspace(1)* %out, float %in) {
-entry:
- %0 = fadd float 5.0, %in
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-; Make sure inline literals are folded into REG_SEQUENCE instructions.
-; CHECK: {{^}}inline_literal_reg_sequence:
-; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
-; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
-; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
-; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
-
-define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) {
-entry:
- store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; CHECK: {{^}}inline_literal_dot4:
-; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
-; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
-; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
-; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
-define void @inline_literal_dot4(float addrspace(1)* %out) {
-entry:
- %0 = call float @llvm.AMDGPU.dp4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
-
-attributes #1 = { readnone }
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.abs.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.abs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.abs.ll (removed)
@@ -1,49 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.abs(i32) nounwind readnone
-
-; Legacy name
-declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_abs_i32:
-; SI: s_sub_i32
-; SI: s_max_i32
-; SI: s_endpgm
-
-; EG: SUB_INT
-; EG: MAX_INT
-define void @s_abs_i32(i32 addrspace(1)* %out, i32 %src) nounwind {
- %abs = call i32 @llvm.AMDGPU.abs(i32 %src) nounwind readnone
- store i32 %abs, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_abs_i32:
-; SI: v_sub_i32_e32
-; SI: v_max_i32_e32
-; SI: s_endpgm
-
-; EG: SUB_INT
-; EG: MAX_INT
-define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
- %val = load i32, i32 addrspace(1)* %src, align 4
- %abs = call i32 @llvm.AMDGPU.abs(i32 %val) nounwind readnone
- store i32 %abs, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}abs_i32_legacy_amdil:
-; SI: v_sub_i32_e32
-; SI: v_max_i32_e32
-; SI: s_endpgm
-
-; EG: SUB_INT
-; EG: MAX_INT
-define void @abs_i32_legacy_amdil(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
- %val = load i32, i32 addrspace(1)* %src, align 4
- %abs = call i32 @llvm.AMDIL.abs.i32(i32 %val) nounwind readnone
- store i32 %abs, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.global.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test_barrier_global:
-; EG: GROUP_BARRIER
-; SI: buffer_store_dword
-; SI: s_waitcnt
-; SI: s_barrier
-
-define void @test_barrier_global(i32 addrspace(1)* %out) {
-entry:
- %0 = call i32 @llvm.r600.read.tidig.x()
- %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0
- store i32 %0, i32 addrspace(1)* %1
- call void @llvm.AMDGPU.barrier.global()
- %2 = call i32 @llvm.r600.read.local.size.x()
- %3 = sub i32 %2, 1
- %4 = sub i32 %3, %0
- %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4
- %6 = load i32, i32 addrspace(1)* %5
- store i32 %6, i32 addrspace(1)* %1
- ret void
-}
-
-declare void @llvm.AMDGPU.barrier.global()
-
-declare i32 @llvm.r600.read.tidig.x() #0
-declare i32 @llvm.r600.read.local.size.x() #0
-
-attributes #0 = { readnone }
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll (removed)
@@ -1,31 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FUNC-LABEL: {{^}}test_barrier_local:
-; EG: GROUP_BARRIER
-
-; SI: buffer_store_dword
-; SI: s_waitcnt
-; SI: s_barrier
-
-define void @test_barrier_local(i32 addrspace(1)* %out) {
-entry:
- %0 = call i32 @llvm.r600.read.tidig.x()
- %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0
- store i32 %0, i32 addrspace(1)* %1
- call void @llvm.AMDGPU.barrier.local()
- %2 = call i32 @llvm.r600.read.local.size.x()
- %3 = sub i32 %2, 1
- %4 = sub i32 %3, %0
- %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4
- %6 = load i32, i32 addrspace(1)* %5
- store i32 %6, i32 addrspace(1)* %1
- ret void
-}
-
-declare void @llvm.AMDGPU.barrier.local()
-
-declare i32 @llvm.r600.read.tidig.x() #0
-declare i32 @llvm.r600.read.local.size.x() #0
-
-attributes #0 = { readnone }
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll (removed)
@@ -1,437 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}bfe_i32_arg_arg_arg:
-; SI: v_bfe_i32
-; EG: BFE_INT
-; EG: encoding: [{{[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+}},0xac
-define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_arg_arg_imm:
-; SI: v_bfe_i32
-; EG: BFE_INT
-define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 123) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_arg_imm_arg:
-; SI: v_bfe_i32
-; EG: BFE_INT
-define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 123, i32 %src2) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_imm_arg_arg:
-; SI: v_bfe_i32
-; EG: BFE_INT
-define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 123, i32 %src1, i32 %src2) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_bfe_print_arg:
-; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8
-define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind {
- %load = load i32, i32 addrspace(1)* %src0, align 4
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_reg_offset:
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_arg_0_width_imm_offset:
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 8, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_6:
-; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
-; SI: s_endpgm
-define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 1, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_7:
-; SI-NOT: shl
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 0, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_8:
-; SI: buffer_load_dword
-; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
-; SI: s_endpgm
-define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_9:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_10:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_11:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_12:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_13:
-; SI: v_ashrrev_i32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = ashr i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_test_14:
-; SI-NOT: lshr
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = lshr i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_0:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 0) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_1:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 12334, i32 0, i32 0) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_2:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_3:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 1, i32 0, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_4:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 0, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_5:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 7, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_6:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0xffffff80
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 0, i32 8) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_7:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 0, i32 8) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_8:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 6, i32 8) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_9:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65536, i32 16, i32 8) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_10:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65535, i32 16, i32 16) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_11:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -6
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 4) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_12:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 31, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_13:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 131070, i32 16, i32 16) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_14:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 2, i32 30) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_15:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 28) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_16:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_17:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 1, i32 31) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_i32_constant_fold_test_18:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
- %bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 31, i32 1) nounwind readnone
- store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_sext_in_reg_i24:
-; SI: buffer_load_dword [[LOAD:v[0-9]+]],
-; SI-NOT: v_lshl
-; SI-NOT: v_ashr
-; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
-; SI: buffer_store_dword [[BFE]],
-define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
- %shl = shl i32 %bfe, 8
- %ashr = ashr i32 %shl, 8
- store i32 %ashr, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: @simplify_demanded_bfe_sdiv
-; SI: buffer_load_dword [[LOAD:v[0-9]+]]
-; SI: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
-; SI: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
-; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]]
-; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
-; SI: buffer_store_dword [[TMP2]]
-define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %src = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone
- %div = sdiv i32 %bfe, 2
- store i32 %div, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll (removed)
@@ -1,627 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}bfe_u32_arg_arg_arg:
-; SI: v_bfe_u32
-; EG: BFE_UINT
-define void @bfe_u32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_arg_arg_imm:
-; SI: v_bfe_u32
-; EG: BFE_UINT
-define void @bfe_u32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 123) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_arg_imm_arg:
-; SI: v_bfe_u32
-; EG: BFE_UINT
-define void @bfe_u32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 123, i32 %src2) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_imm_arg_arg:
-; SI: v_bfe_u32
-; EG: BFE_UINT
-define void @bfe_u32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 123, i32 %src1, i32 %src2) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_reg_offset:
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 %src1, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_arg_0_width_imm_offset:
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %src0, i32 8, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zextload_i8:
-; SI: buffer_load_ubyte
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind {
- %load = load i8, i8 addrspace(1)* %in
- %ext = zext i8 %load to i32
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI-NEXT: v_and_b32_e32
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 255
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI-NEXT: v_and_b32_e32
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 65535
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 0, i32 16)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_1:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI: bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i8_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 255
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 1, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_3:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0xf8
-; SI-NEXT: bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i8_offset_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 255
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 3, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8_offset_7:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI-NEXT: v_and_b32_e32 {{v[0-9]+}}, 0x80
-; SI-NEXT: bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i8_offset_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 255
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 7, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i16_offset_8:
-; SI: buffer_load_dword
-; SI: v_add_i32
-; SI-NEXT: bfe
-; SI: s_endpgm
-define void @bfe_u32_zext_in_reg_i16_offset_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %load = load i32, i32 addrspace(1)* %in, align 4
- %add = add i32 %load, 1
- %ext = and i32 %add, 65535
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %ext, i32 8, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_1:
-; SI: buffer_load_dword
-; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}}
-; SI: s_endpgm
-; EG: AND_INT T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, 1,
-define void @bfe_u32_test_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 0, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-define void @bfe_u32_test_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-define void @bfe_u32_test_3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_4:
-; SI-NOT: lshl
-; SI-NOT: shr
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-define void @bfe_u32_test_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %shr = lshr i32 %shl, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_5:
-; SI: buffer_load_dword
-; SI-NOT: lshl
-; SI-NOT: shr
-; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1
-; SI: s_endpgm
-define void @bfe_u32_test_5(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %shr = ashr i32 %shl, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shr, i32 0, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_6:
-; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
-; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
-; SI: s_endpgm
-define void @bfe_u32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 1, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_7:
-; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 0, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_8:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = shl i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_9:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_10:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 1, i32 31)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_11:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 8, i32 24)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_12:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_lshrrev_b32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %x, i32 24, i32 8)
- store i32 %bfe, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_13:
-; V_ASHRREV_U32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = ashr i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_test_14:
-; SI-NOT: lshr
-; SI-NOT: {{[^@]}}bfe
-; SI: s_endpgm
-define void @bfe_u32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %x = load i32, i32 addrspace(1)* %in, align 4
- %shl = lshr i32 %x, 31
- %bfe = call i32 @llvm.AMDGPU.bfe.u32(i32 %shl, i32 31, i32 1)
- store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_0:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_1:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 12334, i32 0, i32 0) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_2:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 0, i32 0, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_3:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 1, i32 0, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_4:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 0, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_5:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 7, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_6:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x80
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 128, i32 0, i32 8) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_7:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 0, i32 8) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_8:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 127, i32 6, i32 8) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_9:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65536, i32 16, i32 8) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_10:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 65535, i32 16, i32 16) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_11:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 4) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_12:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 31, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_13:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 131070, i32 16, i32 16) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_14:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 40
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 2, i32 30) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_15:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 10
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 160, i32 4, i32 28) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_16:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 4294967295, i32 1, i32 7) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_17:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0x7f
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 1, i32 31) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfe_u32_constant_fold_test_18:
-; SI-NOT: {{[^@]}}bfe
-; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
-; SI: buffer_store_dword [[VREG]],
-; SI: s_endpgm
-; EG-NOT: BFE
-define void @bfe_u32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 255, i32 31, i32 1) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Make sure that SimplifyDemandedBits doesn't cause the and to be
-; reduced to the bits demanded by the bfe.
-
-; XXX: The operand to v_bfe_u32 could also just directly be the load register.
-; FUNC-LABEL: {{^}}simplify_bfe_u32_multi_use_arg:
-; SI: buffer_load_dword [[ARG:v[0-9]+]]
-; SI: v_and_b32_e32 [[AND:v[0-9]+]], 63, [[ARG]]
-; SI: v_bfe_u32 [[BFE:v[0-9]+]], [[AND]], 2, 2
-; SI-DAG: buffer_store_dword [[AND]]
-; SI-DAG: buffer_store_dword [[BFE]]
-; SI: s_endpgm
-define void @simplify_bfe_u32_multi_use_arg(i32 addrspace(1)* %out0,
- i32 addrspace(1)* %out1,
- i32 addrspace(1)* %in) nounwind {
- %src = load i32, i32 addrspace(1)* %in, align 4
- %and = and i32 %src, 63
- %bfe_u32 = call i32 @llvm.AMDGPU.bfe.u32(i32 %and, i32 2, i32 2) nounwind readnone
- store i32 %bfe_u32, i32 addrspace(1)* %out0, align 4
- store i32 %and, i32 addrspace(1)* %out1, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}lshr_and:
-; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
-; SI: buffer_store_dword
-define void @lshr_and(i32 addrspace(1)* %out, i32 %a) nounwind {
- %b = lshr i32 %a, 6
- %c = and i32 %b, 7
- store i32 %c, i32 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_lshr_and:
-; SI: v_bfe_u32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}, 3
-; SI: buffer_store_dword
-define void @v_lshr_and(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
- %c = lshr i32 %a, %b
- %d = and i32 %c, 7
- store i32 %d, i32 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}and_lshr:
-; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
-; SI: buffer_store_dword
-define void @and_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
- %b = and i32 %a, 448
- %c = lshr i32 %b, 6
- store i32 %c, i32 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}and_lshr2:
-; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x30006
-; SI: buffer_store_dword
-define void @and_lshr2(i32 addrspace(1)* %out, i32 %a) nounwind {
- %b = and i32 %a, 511
- %c = lshr i32 %b, 6
- store i32 %c, i32 addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}shl_lshr:
-; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x150002
-; SI: buffer_store_dword
-define void @shl_lshr(i32 addrspace(1)* %out, i32 %a) nounwind {
- %b = shl i32 %a, 9
- %c = lshr i32 %b, 11
- store i32 %c, i32 addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfi.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfi.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfi.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.bfi(i32, i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}bfi_arg_arg_arg:
-; SI: v_bfi_b32
-; EG: BFI_INT
-define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
- %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
- store i32 %bfi, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfi_arg_arg_imm:
-; SI: v_bfi_b32
-; EG: BFI_INT
-define void @bfi_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 123) nounwind readnone
- store i32 %bfi, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfi_arg_imm_arg:
-; SI: v_bfi_b32
-; EG: BFI_INT
-define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
- %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 123, i32 %src2) nounwind readnone
- store i32 %bfi, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfi_imm_arg_arg:
-; SI: v_bfi_b32
-; EG: BFI_INT
-define void @bfi_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
- %bfi = call i32 @llvm.AMDGPU.bfi(i32 123, i32 %src1, i32 %src2) nounwind readnone
- store i32 %bfi, i32 addrspace(1)* %out, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfm.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfm.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.bfm.ll (removed)
@@ -1,60 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}bfm_arg_arg:
-; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
-; EG: BFM_INT
-define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone
- store i32 %bfm, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfm_arg_imm:
-; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x7b
-; EG: BFM_INT
-define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind {
- %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone
- store i32 %bfm, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfm_imm_arg:
-; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, {{s[0-9]+}}
-; EG: BFM_INT
-define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind {
- %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone
- store i32 %bfm, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfm_imm_imm:
-; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, 0x1c8
-; EG: BFM_INT
-define void @bfm_imm_imm(i32 addrspace(1)* %out) nounwind {
- %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone
- store i32 %bfm, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfm_pattern:
-; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
-define void @bfm_pattern(i32 addrspace(1)* %out, i32 %x, i32 %y) {
- %a = shl i32 1, %x
- %b = sub i32 %a, 1
- %c = shl i32 %b, %y
- store i32 %c, i32 addrspace(1)* %out
- ret void
-}
-
-; FUNC-LABEL: {{^}}bfm_pattern_simple:
-; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0
-define void @bfm_pattern_simple(i32 addrspace(1)* %out, i32 %x) {
- %a = shl i32 1, %x
- %b = sub i32 %a, 1
- store i32 %b, i32 addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.brev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.brev.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.brev.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.brev.ll (removed)
@@ -1,28 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.brev(i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_brev_i32:
-; SI: s_load_dword [[VAL:s[0-9]+]],
-; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
-define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
- %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone
- store i32 %ctlz, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_brev_i32:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_bfrev_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
- %val = load i32, i32 addrspace(1)* %valptr, align 4
- %ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone
- store i32 %ctlz, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.clamp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.clamp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.clamp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.clamp.ll (removed)
@@ -1,67 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.fabs.f32(float) nounwind readnone
-declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
-declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone
-
-; FUNC-LABEL: {{^}}clamp_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-
-; EG: MOV_SAT
-define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fabs_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fabs, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fneg_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fneg_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fneg = fsub float -0.0, %src
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_fneg_fabs_0_1_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
- %src.fabs = call float @llvm.fabs.f32(float %src) nounwind readnone
- %src.fneg.fabs = fsub float -0.0, %src.fabs
- %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}clamp_0_1_amdil_legacy_f32:
-; SI: s_load_dword [[ARG:s[0-9]+]],
-; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
-; SI: buffer_store_dword [[RESULT]]
-define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
- %clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
- store float %clamp, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll (removed)
@@ -1,497 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
-declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
-declare i32 @llvm.r600.read.tidig.x() #1
-declare float @llvm.fabs.f32(float) #1
-declare double @llvm.fabs.f64(double) #1
-
-; SI-LABEL: {{^}}test_class_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fabs_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
- %a.fabs = call float @llvm.fabs.f32(float %a) #1
- %result = call i1 @llvm.AMDGPU.class.f32(float %a.fabs, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fneg_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fneg_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
- %a.fneg = fsub float -0.0, %a
- %result = call i1 @llvm.AMDGPU.class.f32(float %a.fneg, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fneg_fabs_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fneg_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
- %a.fabs = call float @llvm.fabs.f32(float %a) #1
- %a.fneg.fabs = fsub float -0.0, %a.fabs
- %result = call i1 @llvm.AMDGPU.class.f32(float %a.fneg.fabs, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_1_f32:
-; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 1{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_1_f32(i32 addrspace(1)* %out, float %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_64_f32:
-; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 64{{$}}
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_64_f32(i32 addrspace(1)* %out, float %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 64) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Set all 10 bits of mask
-; SI-LABEL: {{^}}test_class_full_mask_f32:
-; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}}
-; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_full_mask_f32(i32 addrspace(1)* %out, float %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1023) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_9bit_mask_f32:
-; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
-; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_9bit_mask_f32(i32 addrspace(1)* %out, float %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 511) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}v_test_class_full_mask_f32:
-; SI-DAG: buffer_load_dword [[VA:v[0-9]+]]
-; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
-; SI: v_cmp_class_f32_e32 vcc, [[VA]], [[MASK]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 511) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f32:
-; SI-DAG: buffer_load_dword [[VB:v[0-9]+]]
-; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %b = load i32, i32 addrspace(1)* %gep.in
-
- %result = call i1 @llvm.AMDGPU.class.f32(float 1.0, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; FIXME: Why isn't this using a literal constant operand?
-; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f32:
-; SI-DAG: buffer_load_dword [[VB:v[0-9]+]]
-; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
-; SI: v_cmp_class_f32_e32 vcc, [[VK]], [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_lit_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %b = load i32, i32 addrspace(1)* %gep.in
-
- %result = call i1 @llvm.AMDGPU.class.f32(float 1024.0, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_f64:
-; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 {
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fabs_f64:
-; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 {
- %a.fabs = call double @llvm.fabs.f64(double %a) #1
- %result = call i1 @llvm.AMDGPU.class.f64(double %a.fabs, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fneg_f64:
-; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fneg_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 {
- %a.fneg = fsub double -0.0, %a
- %result = call i1 @llvm.AMDGPU.class.f64(double %a.fneg, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_fneg_fabs_f64:
-; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_fneg_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 {
- %a.fabs = call double @llvm.fabs.f64(double %a) #1
- %a.fneg.fabs = fsub double -0.0, %a.fabs
- %result = call i1 @llvm.AMDGPU.class.f64(double %a.fneg.fabs, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_1_f64:
-; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 1{{$}}
-; SI: s_endpgm
-define void @test_class_1_f64(i32 addrspace(1)* %out, double %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 1) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_64_f64:
-; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 64{{$}}
-; SI: s_endpgm
-define void @test_class_64_f64(i32 addrspace(1)* %out, double %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 64) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; Set all 9 bits of mask
-; SI-LABEL: {{^}}test_class_full_mask_f64:
-; SI: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
-; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[MASK]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI-NEXT: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_full_mask_f64(i32 addrspace(1)* %out, double %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 511) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}v_test_class_full_mask_f64:
-; SI-DAG: buffer_load_dwordx2 [[VA:v\[[0-9]+:[0-9]+\]]]
-; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
-; SI: v_cmp_class_f64_e32 vcc, [[VA]], [[MASK]]
-; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load double, double addrspace(1)* %in
-
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 511) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f64:
-; XSI: v_cmp_class_f64_e32 vcc, 1.0,
-; SI: v_cmp_class_f64_e32 vcc,
-; SI: s_endpgm
-define void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %b = load i32, i32 addrspace(1)* %gep.in
-
- %result = call i1 @llvm.AMDGPU.class.f64(double 1.0, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f64:
-; SI: v_cmp_class_f64_e32 vcc, s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
-; SI: s_endpgm
-define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %b = load i32, i32 addrspace(1)* %gep.in
-
- %result = call i1 @llvm.AMDGPU.class.f64(double 1024.0, i32 %b) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_fold_or_class_f32_0:
-; SI-NOT: v_cmp_class
-; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 3{{$}}
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 3) #1
- %or = or i1 %class0, %class1
-
- %sext = sext i1 %or to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_fold_or3_class_f32_0:
-; SI-NOT: v_cmp_class
-; SI: v_cmp_class_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
- %class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
- %or.0 = or i1 %class0, %class1
- %or.1 = or i1 %or.0, %class2
-
- %sext = sext i1 %or.1 to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_fold_or_all_tests_class_f32_0:
-; SI-NOT: v_cmp_class
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}}
-; SI: v_cmp_class_f32_e32 vcc, v{{[0-9]+}}, [[MASK]]{{$}}
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
- %class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
- %class3 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1
- %class4 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 16) #1
- %class5 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 32) #1
- %class6 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 64) #1
- %class7 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 128) #1
- %class8 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 256) #1
- %class9 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 512) #1
- %or.0 = or i1 %class0, %class1
- %or.1 = or i1 %or.0, %class2
- %or.2 = or i1 %or.1, %class3
- %or.3 = or i1 %or.2, %class4
- %or.4 = or i1 %or.3, %class5
- %or.5 = or i1 %or.4, %class6
- %or.6 = or i1 %or.5, %class7
- %or.7 = or i1 %or.6, %class8
- %or.8 = or i1 %or.7, %class9
- %sext = sext i1 %or.8 to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_fold_or_class_f32_1:
-; SI-NOT: v_cmp_class
-; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 12{{$}}
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1
- %or = or i1 %class0, %class1
-
- %sext = sext i1 %or to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_fold_or_class_f32_2:
-; SI-NOT: v_cmp_class
-; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
-define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
- %or = or i1 %class0, %class1
-
- %sext = sext i1 %or to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_no_fold_or_class_f32_0:
-; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 4{{$}}
-; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 8{{$}}
-; SI: s_or_b64
-; SI: s_endpgm
-define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 {
- %tid = call i32 @llvm.r600.read.tidig.x() #1
- %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %a = load float, float addrspace(1)* %gep.in
-
- %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
- %class1 = call i1 @llvm.AMDGPU.class.f32(float %b, i32 8) #1
- %or = or i1 %class0, %class1
-
- %sext = sext i1 %or to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_0_f32:
-; SI-NOT: v_cmp_class
-; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_class_0_f64:
-; SI-NOT: v_cmp_class
-; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
-; SI: buffer_store_dword [[RESULT]]
-; SI: s_endpgm
-define void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 {
- %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 0) #1
- %sext = sext i1 %result to i32
- store i32 %sext, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cube.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cube.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cube.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cube.ll (removed)
@@ -1,59 +0,0 @@
-
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}cube:
-; CHECK: CUBE T{{[0-9]}}.X
-; CHECK: CUBE T{{[0-9]}}.Y
-; CHECK: CUBE T{{[0-9]}}.Z
-; CHECK: CUBE * T{{[0-9]}}.W
-define void @cube() #0 {
-main_body:
- %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %1 = extractelement <4 x float> %0, i32 3
- %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %3 = extractelement <4 x float> %2, i32 0
- %4 = fdiv float %3, %1
- %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %6 = extractelement <4 x float> %5, i32 1
- %7 = fdiv float %6, %1
- %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
- %9 = extractelement <4 x float> %8, i32 2
- %10 = fdiv float %9, %1
- %11 = insertelement <4 x float> undef, float %4, i32 0
- %12 = insertelement <4 x float> %11, float %7, i32 1
- %13 = insertelement <4 x float> %12, float %10, i32 2
- %14 = insertelement <4 x float> %13, float 1.000000e+00, i32 3
- %15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %14)
- %16 = extractelement <4 x float> %15, i32 0
- %17 = extractelement <4 x float> %15, i32 1
- %18 = extractelement <4 x float> %15, i32 2
- %19 = extractelement <4 x float> %15, i32 3
- %20 = call float @fabs(float %18)
- %21 = fdiv float 1.000000e+00, %20
- %22 = fmul float %16, %21
- %23 = fadd float %22, 1.500000e+00
- %24 = fmul float %17, %21
- %25 = fadd float %24, 1.500000e+00
- %26 = insertelement <4 x float> undef, float %25, i32 0
- %27 = insertelement <4 x float> %26, float %23, i32 1
- %28 = insertelement <4 x float> %27, float %19, i32 2
- %29 = insertelement <4 x float> %28, float %25, i32 3
- %30 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %29, i32 16, i32 0, i32 4)
- call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0)
- ret void
-}
-
-; Function Attrs: readnone
-declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1
-
-; Function Attrs: readnone
-declare float @fabs(float) #1
-
-; Function Attrs: readnone
-declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
-attributes #1 = { readnone }
-
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll (removed)
@@ -1,43 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone
-declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone
-declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone
-declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
-
-; SI-LABEL: {{^}}test_unpack_byte0_to_float:
-; SI: v_cvt_f32_ubyte0
-define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_unpack_byte1_to_float:
-; SI: v_cvt_f32_ubyte1
-define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_unpack_byte2_to_float:
-; SI: v_cvt_f32_ubyte2
-define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_unpack_byte3_to_float:
-; SI: v_cvt_f32_ubyte3
-define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %val = load i32, i32 addrspace(1)* %in, align 4
- %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
- store float %cvt, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll (removed)
@@ -1,31 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
-
-declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone
-declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone
-
-; GCN-LABEL: {{^}}test_div_fixup_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
-; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
-; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
-; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
- %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fixup_f64:
-; GCN: v_div_fixup_f64
-define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind {
- %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll (removed)
@@ -1,179 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-
-; FIXME: Enable for VI.
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-declare void @llvm.AMDGPU.barrier.global() nounwind noduplicate
-declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone
-declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
-
-; GCN-LABEL: {{^}}test_div_fmas_f32:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
-; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
-; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
-; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
-; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
-; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
-define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0:
-; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
-; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
-; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2:
-; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
-; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
-; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
-; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f64:
-; GCN: v_div_fmas_f64
-define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
- %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
-; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
-; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
- %cmp = icmp eq i32 %i, 0
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
-; SI: s_mov_b64 vcc, 0
-; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
-; SI: s_mov_b64 vcc, -1
-; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
-; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
-
-; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
-; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
-; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
-; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
-; SI: s_endpgm
-define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
- %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
-
- %a = load float, float addrspace(1)* %gep.a
- %b = load float, float addrspace(1)* %gep.b
- %c = load float, float addrspace(1)* %gep.c
-
- %cmp0 = icmp eq i32 %tid, 0
- %cmp1 = icmp ne i32 %d, 0
- %and = and i1 %cmp0, %cmp1
-
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
- store float %result, float addrspace(1)* %gep.out, align 4
- ret void
-}
-
-; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
-; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}}
-; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
-; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]]
-
-; SI: buffer_load_dword [[LOAD:v[0-9]+]]
-; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]]
-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
-
-
-; SI: BB9_2:
-; SI: s_or_b64 exec, exec, [[SAVE]]
-; SI: v_cmp_ne_i32_e32 vcc, 0, v0
-; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
-; SI: buffer_store_dword
-; SI: s_endpgm
-define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
-entry:
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
- %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
- %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
-
- %a = load float, float addrspace(1)* %gep.a
- %b = load float, float addrspace(1)* %gep.b
- %c = load float, float addrspace(1)* %gep.c
-
- %cmp0 = icmp eq i32 %tid, 0
- br i1 %cmp0, label %bb, label %exit
-
-bb:
- %val = load i32, i32 addrspace(1)* %dummy
- %cmp1 = icmp ne i32 %val, 0
- br label %exit
-
-exit:
- %cond = phi i1 [false, %entry], [%cmp1, %bb]
- %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
- store float %result, float addrspace(1)* %gep.out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll (removed)
@@ -1,364 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind readnone
-declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone
-declare float @llvm.fabs.f32(float) nounwind readnone
-
-; SI-LABEL @test_div_scale_f32_1:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_2:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_1:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_1:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
-
- %a = load double, double addrspace(1)* %gep.0, align 8
- %b = load double, double addrspace(1)* %gep.1, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_scalar_num_1:
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
-; SI-DAG: s_load_dword [[A:s[0-9]+]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
-
- %b = load float, float addrspace(1)* %gep, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_scalar_num_2:
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
-; SI-DAG: s_load_dword [[A:s[0-9]+]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
-
- %b = load float, float addrspace(1)* %gep, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_scalar_den_1:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
-; SI-DAG: s_load_dword [[B:s[0-9]+]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
-
- %a = load float, float addrspace(1)* %gep, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_scalar_den_2:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
-; SI-DAG: s_load_dword [[B:s[0-9]+]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
-
- %a = load float, float addrspace(1)* %gep, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_scalar_num_1:
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
-; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
-
- %b = load double, double addrspace(1)* %gep, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_scalar_num_2:
-; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
-
- %b = load double, double addrspace(1)* %gep, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_scalar_den_1:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
-; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
-
- %a = load double, double addrspace(1)* %gep, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_scalar_den_2:
-; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
-; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
-
- %a = load double, double addrspace(1)* %gep, align 8
-
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_all_scalar_1:
-; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind {
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_all_scalar_2:
-; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
-; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind {
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_all_scalar_1:
-; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]
-; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}}
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind {
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f64_all_scalar_2:
-; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
-; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]
-; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]]
-; SI: buffer_store_dwordx2 [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind {
- %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
- %result0 = extractvalue { double, i1 } %result, 0
- store double %result0, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_inline_imm_num:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[A]], 1.0
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %a = load float, float addrspace(1)* %gep.0, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_inline_imm_den:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], 2.0, 2.0, [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %a = load float, float addrspace(1)* %gep.0, align 4
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_fabs_num:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], |[[A]]|
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a.fabs, float %b, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL @test_div_scale_f32_fabs_den:
-; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
-; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], |[[B]]|, |[[B]]|, [[A]]
-; SI: buffer_store_dword [[RESULT0]]
-; SI: s_endpgm
-define void @test_div_scale_f32_fabs_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
- %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
-
- %a = load float, float addrspace(1)* %gep.0, align 4
- %b = load float, float addrspace(1)* %gep.1, align 4
-
- %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
-
- %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b.fabs, i1 false) nounwind readnone
- %result0 = extractvalue { float, i1 } %result, 0
- store float %result0, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll (removed)
@@ -1,28 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.flbit.i32(i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}s_flbit:
-; SI: s_load_dword [[VAL:s[0-9]+]],
-; SI: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
-define void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
- %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
- store i32 %r, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}v_flbit:
-; SI: buffer_load_dword [[VAL:v[0-9]+]],
-; SI: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
-define void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
- %val = load i32, i32 addrspace(1)* %valptr, align 4
- %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
- store i32 %r, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.f64.ll (removed)
@@ -1,60 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
-
-declare double @llvm.fabs.f64(double %Val)
-declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone
-
-; FUNC-LABEL: {{^}}fract_f64:
-; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
-; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
-; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
-; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
-; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
-; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
-; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
-; CI: buffer_store_dwordx2 [[FRC]]
-define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
- %val = load double, double addrspace(1)* %src, align 4
- %fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone
- store double %fract, double addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fract_f64_neg:
-; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
-; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
-; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
-; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
-; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
-; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
-; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
-; CI: buffer_store_dwordx2 [[FRC]]
-define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
- %val = load double, double addrspace(1)* %src, align 4
- %neg = fsub double 0.0, %val
- %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
- store double %fract, double addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fract_f64_neg_abs:
-; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
-; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
-; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
-; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
-; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
-; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
-; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
-; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
-; CI: buffer_store_dwordx2 [[FRC]]
-define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
- %val = load double, double addrspace(1)* %src, align 4
- %abs = call double @llvm.fabs.f64(double %val)
- %neg = fsub double 0.0, %abs
- %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
- store double %fract, double addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.fract.ll (removed)
@@ -1,65 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.fabs.f32(float %Val)
-declare float @llvm.AMDGPU.fract.f32(float) nounwind readnone
-
-; Legacy name
-declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}fract_f32:
-; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
-; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
-; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
-; GCN: buffer_store_dword [[RESULT]]
-; EG: FRACT
-define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
- %val = load float, float addrspace(1)* %src, align 4
- %fract = call float @llvm.AMDGPU.fract.f32(float %val) nounwind readnone
- store float %fract, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fract_f32_legacy_amdil:
-; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
-; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
-; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
-; GCN: buffer_store_dword [[RESULT]]
-; EG: FRACT
-define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
- %val = load float, float addrspace(1)* %src, align 4
- %fract = call float @llvm.AMDIL.fraction.f32(float %val) nounwind readnone
- store float %fract, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fract_f32_neg:
-; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
-; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -[[INPUT:v[0-9]+]]
-; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]]
-; GCN: buffer_store_dword [[RESULT]]
-; EG: FRACT
-define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
- %val = load float, float addrspace(1)* %src, align 4
- %neg = fsub float 0.0, %val
- %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
- store float %fract, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}fract_f32_neg_abs:
-; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
-; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
-; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]]
-; GCN: buffer_store_dword [[RESULT]]
-; EG: FRACT
-define void @fract_f32_neg_abs(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
- %val = load float, float addrspace(1)* %src, align 4
- %abs = call float @llvm.fabs.f32(float %val)
- %neg = fsub float 0.0, %abs
- %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
- store float %fract, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imad24.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imad24.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imad24.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imad24.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-; FIXME: Store of i32 seems to be broken pre-EG somehow?
-
-declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}test_imad24:
-; SI: v_mad_i32_i24
-; CM: MULADD_INT24
-; R600: MULLO_INT
-; R600: ADD_INT
-define void @test_imad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
- %mad = call i32 @llvm.AMDGPU.imad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
- store i32 %mad, i32 addrspace(1)* %out, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imax.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imax.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imax.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}vector_imax:
-; SI: v_max_i32_e32
-define void @vector_imax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
-main_body:
- %load = load i32, i32 addrspace(1)* %in, align 4
- %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %load)
- %bc = bitcast i32 %max to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}scalar_imax:
-; SI: s_max_i32
-define void @scalar_imax(i32 %p0, i32 %p1) #0 {
-entry:
- %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1)
- %bc = bitcast i32 %max to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; Function Attrs: readnone
-declare i32 @llvm.AMDGPU.imax(i32, i32) #1
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
-
-!0 = !{!"const", null, i32 1}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imin.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imin.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imin.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}vector_imin:
-; SI: v_min_i32_e32
-define void @vector_imin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
-main_body:
- %load = load i32, i32 addrspace(1)* %in, align 4
- %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %load)
- %bc = bitcast i32 %min to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}scalar_imin:
-; SI: s_min_i32
-define void @scalar_imin(i32 %p0, i32 %p1) #0 {
-entry:
- %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1)
- %bc = bitcast i32 %min to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; Function Attrs: readnone
-declare i32 @llvm.AMDGPU.imin(i32, i32) #1
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
-
-!0 = !{!"const", null, i32 1}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imul24.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imul24.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imul24.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.imul24.ll (removed)
@@ -1,16 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}test_imul24:
-; SI: v_mul_i32_i24
-; CM: MUL_INT24
-; R600: MULLO_INT
-define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone
- store i32 %mul, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.kill.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.kill.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.kill.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}kill_gs_const:
-; SI-NOT: v_cmpx_le_f32
-; SI: s_mov_b64 exec, 0
-
-define void @kill_gs_const() #0 {
-main_body:
- %0 = icmp ule i32 0, 3
- %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
- call void @llvm.AMDGPU.kill(float %1)
- %2 = icmp ule i32 3, 0
- %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
- call void @llvm.AMDGPU.kill(float %3)
- ret void
-}
-
-; SI-LABEL: {{^}}kill_vcc_implicit_def:
-; SI-NOT: v_cmp_gt_f32_e32 vcc,
-; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
-; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
-; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
-define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
-entry:
- %tmp0 = fcmp olt float %13, 0.0
- call void @llvm.AMDGPU.kill(float %14)
- %tmp1 = select i1 %tmp0, float 1.0, float 0.0
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
- ret void
-}
-
-declare void @llvm.AMDGPU.kill(float)
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { "ShaderType"="2" }
-attributes #1 = { "ShaderType"="0" }
-
-!0 = !{!"const", null, i32 1}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare float @llvm.AMDGPU.ldexp.f32(float, i32) nounwind readnone
-declare double @llvm.AMDGPU.ldexp.f64(double, i32) nounwind readnone
-
-; SI-LABEL: {{^}}test_ldexp_f32:
-; SI: v_ldexp_f32
-; SI: s_endpgm
-define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind {
- %result = call float @llvm.AMDGPU.ldexp.f32(float %a, i32 %b) nounwind readnone
- store float %result, float addrspace(1)* %out, align 4
- ret void
-}
-
-; SI-LABEL: {{^}}test_ldexp_f64:
-; SI: v_ldexp_f64
-; SI: s_endpgm
-define void @test_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind {
- %result = call double @llvm.AMDGPU.ldexp.f64(double %a, i32 %b) nounwind readnone
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.legacy.rsq.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.AMDGPU.legacy.rsq(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_legacy_f32:
-; SI: v_rsq_legacy_f32_e32
-; EG: RECIPSQRT_IEEE
-define void @rsq_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
- %rsq = call float @llvm.AMDGPU.legacy.rsq(float %src) nounwind readnone
- store float %rsq, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll (removed)
@@ -1,17 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> inreg %reg0) #0 {
- %r0 = extractelement <4 x float> %reg0, i32 0
- %r1 = extractelement <4 x float> %reg0, i32 1
- %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1)
- %vec = insertelement <4 x float> undef, float %r2, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
- ret void
-}
-
-declare float @llvm.AMDGPU.mul(float ,float ) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-
-declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
-declare double @llvm.sqrt.f64(double) nounwind readnone
-
-; FUNC-LABEL: {{^}}rcp_f64:
-; SI: v_rcp_f64_e32
-define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind {
- %rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone
- store double %rcp, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}rcp_pat_f64:
-; SI: v_rcp_f64_e32
-define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
- %rcp = fdiv double 1.0, %src
- store double %rcp, double addrspace(1)* %out, align 8
- ret void
-}
-
-; FUNC-LABEL: {{^}}rsq_rcp_pat_f64:
-; SI-UNSAFE: v_rsq_f64_e32
-; SI-SAFE-NOT: v_rsq_f64_e32
-; SI-SAFE: v_sqrt_f64
-; SI-SAFE: v_rcp_f64
-define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
- %sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone
- %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone
- store double %rcp, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rcp.ll (removed)
@@ -1,50 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; XUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
-
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
-declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
-
-declare float @llvm.sqrt.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rcp_f32:
-; SI: v_rcp_f32_e32
-; EG: RECIP_IEEE
-define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind {
- %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone
- store float %rcp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FIXME: Evergreen only ever does unsafe fp math.
-; FUNC-LABEL: {{^}}rcp_pat_f32:
-
-; SI-SAFE: v_rcp_f32_e32
-; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32
-
-; EG: RECIP_IEEE
-
-define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
- %rcp = fdiv float 1.0, %src
- store float %rcp, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}rsq_rcp_pat_f32:
-; SI-UNSAFE: v_rsq_f32_e32
-; SI-SAFE: v_sqrt_f32_e32
-; SI-SAFE: v_rcp_f32_e32
-
-; EG: RECIPSQRT_IEEE
-define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
- %sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone
- %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone
- store float %rcp, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
-
-declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_clamped_f64:
-; SI: v_rsq_clamp_f64_e32
-
-; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3]
-; TODO: this constant should be folded:
-; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
-; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
-; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
-; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
-; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
-; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
-; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
-
-define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
- %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
- store double %rsq_clamped, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-
-declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_clamped_f32:
-; SI: v_rsq_clamp_f32_e32
-
-; VI: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}}
-; VI: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
-; TODO: this constant should be folded:
-; VI: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff
-; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]]
-
-; EG: RECIPSQRT_CLAMPED
-
-define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind {
- %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone
- store float %rsq_clamped, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.rsq.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_f32:
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32(float addrspace(1)* %out, float %src) nounwind {
- %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone
- store float %rsq, float addrspace(1)* %out, align 4
- ret void
-}
-
-; TODO: Really these should be constant folded
-; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32_constant_4.0(float addrspace(1)* %out) nounwind {
- %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone
- store float %rsq, float addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}rsq_f32_constant_100.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32_constant_100.0(float addrspace(1)* %out) nounwind {
- %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone
- store float %rsq, float addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.tex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.tex.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.tex.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.tex.ll (removed)
@@ -1,42 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:UUNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYYW}} RID:0 SID:0 CT:NNUN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYYZ}} RID:0 SID:0 CT:NNUN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN
-;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
-;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN
-
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %addr = load <4 x float>, <4 x float> addrspace(1)* %in
- %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %addr, i32 0, i32 0, i32 1)
- %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res1, i32 0, i32 0, i32 2)
- %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res2, i32 0, i32 0, i32 3)
- %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res3, i32 0, i32 0, i32 4)
- %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res4, i32 0, i32 0, i32 5)
- %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res5, i32 0, i32 0, i32 6)
- %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res6, i32 0, i32 0, i32 7)
- %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res7, i32 0, i32 0, i32 8)
- %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res8, i32 0, i32 0, i32 9)
- %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res9, i32 0, i32 0, i32 10)
- %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
- %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res11, i32 0, i32 0, i32 12)
- %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res12, i32 0, i32 0, i32 13)
- %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14)
- %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res14, i32 0, i32 0, i32 15)
- %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res15, i32 0, i32 0, i32 16)
- store <4 x float> %res16, <4 x float> addrspace(1)* %out
- ret void
-}
-
-declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-
-declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone
-
-; SI-LABEL: {{^}}test_trig_preop_f64:
-; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]]
-; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
-; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
-define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
- %a = load double, double addrspace(1)* %aptr, align 8
- %b = load i32, i32 addrspace(1)* %bptr, align 4
- %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
-
-; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment:
-; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]],
-; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
-; SI: buffer_store_dwordx2 [[RESULT]],
-; SI: s_endpgm
-define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
- %a = load double, double addrspace(1)* %aptr, align 8
- %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone
- store double %result, double addrspace(1)* %out, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trunc.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trunc.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.trunc.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s
-
-; R600: {{^}}amdgpu_trunc:
-; R600: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z
-; SI: {{^}}amdgpu_trunc:
-; SI: v_trunc_f32
-
-define void @amdgpu_trunc(float addrspace(1)* %out, float %x) {
-entry:
- %0 = call float @llvm.AMDGPU.trunc(float %x)
- store float %0, float addrspace(1)* %out
- ret void
-}
-
-declare float @llvm.AMDGPU.trunc(float ) readnone
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umad24.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umad24.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umad24.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umad24.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=rv770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone
-declare i32 @llvm.r600.read.tidig.x() nounwind readnone
-
-; FUNC-LABEL: {{^}}test_umad24:
-; SI: v_mad_u32_u24
-; EG: MULADD_UINT24
-; R600: MULLO_UINT
-; R600: ADD_INT
-define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
- %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
- store i32 %mad, i32 addrspace(1)* %out, align 4
- ret void
-}
-
-; FUNC-LABEL: {{^}}commute_umad24:
-; SI-DAG: buffer_load_dword [[SRC0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
-; SI-DAG: buffer_load_dword [[SRC2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
-; SI: v_mad_u32_u24 [[RESULT:v[0-9]+]], 4, [[SRC0]], [[SRC2]]
-; SI: buffer_store_dword [[RESULT]]
-define void @commute_umad24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
- %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
- %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %src0.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
- %src2.gep = getelementptr i32, i32 addrspace(1)* %src0.gep, i32 1
-
- %src0 = load i32, i32 addrspace(1)* %src0.gep, align 4
- %src2 = load i32, i32 addrspace(1)* %src2.gep, align 4
- %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone
- store i32 %mad, i32 addrspace(1)* %out.gep, align 4
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umax.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umax.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umax.ll (removed)
@@ -1,48 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}vector_umax:
-; SI: v_max_u32_e32
-define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
-main_body:
- %load = load i32, i32 addrspace(1)* %in, align 4
- %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load)
- %bc = bitcast i32 %max to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}scalar_umax:
-; SI: s_max_u32
-define void @scalar_umax(i32 %p0, i32 %p1) #0 {
-entry:
- %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1)
- %bc = bitcast i32 %max to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}trunc_zext_umax:
-; SI: buffer_load_ubyte [[VREG:v[0-9]+]],
-; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
-; SI-NOT: and
-; SI: buffer_store_short [[RESULT]],
-define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
- %tmp5 = load i8, i8 addrspace(1)* %src, align 1
- %tmp2 = zext i8 %tmp5 to i32
- %tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone
- %tmp4 = trunc i32 %tmp3 to i8
- %tmp6 = zext i8 %tmp4 to i16
- store i16 %tmp6, i16 addrspace(1)* %out, align 2
- ret void
-}
-
-; Function Attrs: readnone
-declare i32 @llvm.AMDGPU.umax(i32, i32) #1
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
-
-!0 = !{!"const", null, i32 1}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umin.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umin.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umin.ll (removed)
@@ -1,48 +0,0 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s
-
-; SI-LABEL: {{^}}vector_umin:
-; SI: v_min_u32_e32
-define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
-main_body:
- %load = load i32, i32 addrspace(1)* %in, align 4
- %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load)
- %bc = bitcast i32 %min to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}scalar_umin:
-; SI: s_min_u32
-define void @scalar_umin(i32 %p0, i32 %p1) #0 {
-entry:
- %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1)
- %bc = bitcast i32 %min to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
- ret void
-}
-
-; SI-LABEL: {{^}}trunc_zext_umin:
-; SI: buffer_load_ubyte [[VREG:v[0-9]+]],
-; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
-; SI-NOT: and
-; SI: buffer_store_short [[RESULT]],
-define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
- %tmp5 = load i8, i8 addrspace(1)* %src, align 1
- %tmp2 = zext i8 %tmp5 to i32
- %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone
- %tmp4 = trunc i32 %tmp3 to i8
- %tmp6 = zext i8 %tmp4 to i16
- store i16 %tmp6, i16 addrspace(1)* %out, align 2
- ret void
-}
-
-; Function Attrs: readnone
-declare i32 @llvm.AMDGPU.umin(i32, i32) #1
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind readnone }
-
-!0 = !{!"const", null, i32 1}
Removed: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umul24.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umul24.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umul24.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.umul24.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
-
-declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone
-
-; FUNC-LABEL: {{^}}test_umul24:
-; SI: v_mul_u32_u24
-; R600: MUL_UINT24
-; R600: MULLO_UINT
-define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
- %mul = call i32 @llvm.AMDGPU.umul24(i32 %src0, i32 %src1) nounwind readnone
- store i32 %mul, i32 addrspace(1)* %out, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.ll?rev=239656&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.ll (removed)
@@ -1,59 +0,0 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
-;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
-
-;GCN-LABEL: {{^}}main:
-;GCN-NOT: s_wqm
-;GCN: s_mov_b32
-;GCN-NEXT: v_interp_mov_f32
-;GCN: v_interp_p1_f32
-;GCN: v_interp_p2_f32
-
-define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
-main_body:
- %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
- %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
- %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
- ret void
-}
-
-; Thest that v_interp_p1 uses different source and destination registers
-; on 16 bank LDS chips.
-
-; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
-; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
-
-define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
-main_body:
- %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
- %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
- %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
- %25 = call float @fabs(float %22)
- %26 = call float @fabs(float %23)
- %27 = call float @fabs(float %24)
- %28 = call i32 @llvm.SI.packf16(float %25, float %26)
- %29 = bitcast i32 %28 to float
- %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
- %31 = bitcast i32 %30 to float
- call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
- ret void
-}
-
-; Function Attrs: readnone
-declare float @fabs(float) #2
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.SI.packf16(float, float) #1
-
-; Function Attrs: nounwind readnone
-declare float @llvm.SI.fs.constant(i32, i32, i32) #1
-
-; Function Attrs: nounwind readnone
-declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { "ShaderType"="0" }
-attributes #1 = { nounwind readnone }
-attributes #2 = { readnone }
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