[PATCH] [AArch64] Match interleaved memory accesses into ldN/stN instructions.

[silviu.baranga at arm.com]

Hi Hao,

Another comment from me as well.

Thanks,
Silviu


================
Comment at: lib/Target/AArch64/AArch64TargetTransformInfo.cpp:415
@@ +414,3 @@
+
+  if (Factor > 1 && Factor < 5 && isTypeLegal(VecTy))
+    return Factor;
----------------
If we get a a legal type here that cannot be matched by the pass (for example v4i8) this will produce the wrong cost.
I think we also need to check that the type size is either 64 or 128.

http://reviews.llvm.org/D10335

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