[llvm] r239522 - [mips][microMIPS] Implement ERET and ERETNC instructions
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Thu Jun 11 03:22:47 PDT 2015
Author: zjovanovic
Date: Thu Jun 11 05:22:46 2015
New Revision: 239522
URL: http://llvm.org/viewvc/llvm-project?rev=239522&view=rev
Log:
[mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=239522&r1=239521&r2=239522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Thu Jun 11 05:22:46 2015
@@ -221,3 +221,22 @@ class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<b
let Inst{20-16} = rt;
let Inst{15-0} = offset;
}
+
+class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x00;
+ let Inst{25-16} = 0x00;
+ let Inst{15-6} = 0x3cd;
+ let Inst{5-0} = 0x3c;
+}
+
+class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x00;
+ let Inst{25-17} = 0x00;
+ let Inst{16-16} = 0x01;
+ let Inst{15-6} = 0x3cd;
+ let Inst{5-0} = 0x3c;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=239522&r1=239521&r2=239522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Thu Jun 11 05:22:46 2015
@@ -40,6 +40,8 @@ class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<
class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
+class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
+class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
@@ -164,6 +166,9 @@ class CLO_CLZ_MMR6_DESC_BASE<string inst
class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
+class ERET_MMR6_DESC : ER_FT<"eret">;
+class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
+
class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
RegisterOperand GPROpnd>
: MMR6Arch<opstr> {
@@ -302,6 +307,9 @@ def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC,
def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
+def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
+def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
+ ISA_MICROMIPS32R6;
def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=239522&r1=239521&r2=239522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jun 11 05:22:46 2015
@@ -1281,7 +1281,9 @@ def SYSCALL : MMRel, SYS_FT<"syscall">,
def TRAP : TrapBase<BREAK>;
def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
+}
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=239522&r1=239521&r2=239522&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Thu Jun 11 05:22:46 2015
@@ -32,17 +32,13 @@
0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332
-# CHECK: balc 14572256
-0xb4 0x37 0x96 0xb8
+0xb4 0x37 0x96 0xb8 # CHECK: balc 14572256
-# CHECK: bc 14572256
-0x94 0x37 0x96 0xb8
+0x94 0x37 0x96 0xb8 # CHECK: bc 14572256
-# CHECK: bitswap $4, $2
-0x00 0x44 0x0b 0x3c
+0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2
-# CHECK: cache 1, 8($5)
-0x20 0x25 0x60 0x08
+0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5)
0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
@@ -52,6 +48,10 @@
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
+0x00 0x00 0xf3 0x7c # CHECK: eret
+
+0x00 0x01 0xf3 0x7c # CHECK: eretnc
+
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
@@ -78,8 +78,7 @@
0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
-# CHECK: pref 1, 8($5)
-0x60 0x25 0x20 0x08
+0x60 0x25 0x20 0x08 # CHECK: pref 1, 8($5)
0x00 0x83 0x11 0x40 # CHECK: seleqz $2, $3, $4
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=239522&r1=239521&r2=239522&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Jun 11 05:22:46 2015
@@ -25,6 +25,8 @@
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98]
+ eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c]
+ eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x26,0x0f]
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