[PATCH] LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned data at -O0/fast-isel (-mno-unaligned-access)

[Alexandros Lamprineas]

Adding -fast-isel to the run line means we're no longer testing the ISelDAG path. Created a new RUN line for fast-isel.


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10360

Files:
  lib/Target/AArch64/AArch64FastISel.cpp
  test/CodeGen/AArch64/arm64-strict-align.ll

Index: test/CodeGen/AArch64/arm64-strict-align.ll
===================================================================
--- test/CodeGen/AArch64/arm64-strict-align.ll
+++ test/CodeGen/AArch64/arm64-strict-align.ll
@@ -1,8 +1,14 @@
 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-no-strict-align | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align | FileCheck %s --check-prefix=CHECK-STRICT
+; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align -fast-isel | FileCheck %s --check-prefix=CHECK-STRICT-FASTISEL
 
 define i32 @f0(i32* nocapture %p) nounwind {
+; CHECK-STRICT-FASTISEL: ldrh [[HIGH:w[0-9]+]], [x0, #2]
+; CHECK-STRICT-FASTISEL: ldrh [[LOW:w[0-9]+]], [x0]
+; CHECK-STRICT-FASTISEL: bfi [[LOW]], [[HIGH]], #16, #16
+; CHECK-STRICT-FASTISEL: ret
+
 ; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]
 ; CHECK-STRICT: ldrh [[LOW:w[0-9]+]], [x0]
 ; CHECK-STRICT: bfi [[LOW]], [[HIGH]], #16, #16
@@ -15,6 +21,10 @@
 }
 
 define i64 @f1(i64* nocapture %p) nounwind {
+; CHECK-STRICT-FASTISEL: ldp w[[LOW:[0-9]+]], w[[HIGH:[0-9]+]], [x0]
+; CHECK-STRICT-FASTISEL: bfi x[[LOW]], x[[HIGH]], #32, #32
+; CHECK-STRICT-FASTISEL: ret
+
 ; CHECK-STRICT:	ldp	w[[LOW:[0-9]+]], w[[HIGH:[0-9]+]], [x0]
 ; CHECK-STRICT: bfi x[[LOW]], x[[HIGH]], #32, #32
 ; CHECK-STRICT:	ret
Index: lib/Target/AArch64/AArch64FastISel.cpp
===================================================================
--- lib/Target/AArch64/AArch64FastISel.cpp
+++ lib/Target/AArch64/AArch64FastISel.cpp
@@ -1678,6 +1678,9 @@
 
 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
                                    bool WantZExt, MachineMemOperand *MMO) {
+  if(!TLI.allowsMisalignedMemoryAccesses(VT))
+    return 0;
+
   // Simplify this down to something we can handle.
   if (!simplifyAddress(Addr, VT))
     return 0;
@@ -1962,6 +1965,9 @@
 
 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
                                 MachineMemOperand *MMO) {
+  if(!TLI.allowsMisalignedMemoryAccesses(VT))
+    return false;
+
   // Simplify this down to something we can handle.
   if (!simplifyAddress(Addr, VT))
     return false;

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