PATCHES: R600/SI: Enable flat instructions on VI
Matt Arsenault
Matthew.Arsenault at amd.com
Mon Jun 8 14:37:28 PDT 2015
On 06/08/2015 01:51 PM, Tom Stellard wrote:
> Hi,
>
> The attached patches add assembler support for FLAT instructions and
> add patterns to match them to global loads/stores on VI. This should
> be enough to get most compute programs working on VI.
>
> -Tom
>
> 0001-R600-SI-Move-flat-instruction-defs-to-CIInstructions.patch
>
>
> From 1e93f12fb3c3e7560a37bdfef1e19e7a6da15aed Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 4 Jun 2015 15:34:50 -0400
> Subject: [PATCH 1/5] R600/SI: Move flat instruction defs to CIInstructions.td
>
> ---
> lib/Target/R600/CIInstructions.td | 110 ++++++++++++++++++++++++++++++++++++++
> lib/Target/R600/SIInstructions.td | 108 -------------------------------------
> 2 files changed, 110 insertions(+), 108 deletions(-)
LGTM
>
> 0002-R600-SI-Define-latency-for-flat-instructions.patch
>
>
> From ee60b2a0004e1d2f443e41a360fcd44d4b4dce68 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 4 Jun 2015 16:48:21 -0400
> Subject: [PATCH 2/5] R600/SI: Define latency for flat instructions
>
> ---
> lib/Target/R600/SIInstrFormats.td | 1 +
> 1 file changed, 1 insertion(+)
>
LGTM
>
> 0003-R600-SI-Add-assembler-support-for-FLAT-instructions.patch
>
>
> From 458dcde606db809d4d76f1caf49b535a3c09e848 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 4 Jun 2015 15:55:56 -0400
> Subject: [PATCH 3/5] R600/SI: Add assembler support for FLAT instructions
>
> - Add glc, slc, and tfe operands to flat instructions
> - Add missing flat instructions
> - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.
> ---
> docs/R600Usage.rst | 5 +
> lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp | 65 ++++
> lib/Target/R600/CIInstructions.td | 125 ++++---
> lib/Target/R600/SIInstrFormats.td | 1 +
> lib/Target/R600/SIInstrInfo.td | 92 +++--
> test/CodeGen/R600/flat-address-space.ll | 2 +-
> test/MC/R600/flat.s | 477 ++++++++++++++++++++++++++
> 7 files changed, 677 insertions(+), 90 deletions(-)
> create mode 100644 test/MC/R600/flat.s
>
> diff --git a/docs/R600Usage.rst b/docs/R600Usage.rst
> index 093cdd7..9bd16f4 100644
> --- a/docs/R600Usage.rst
> +++ b/docs/R600Usage.rst
> @@ -24,6 +24,11 @@ DS Instructions
> ---------------
> All DS instructions are supported.
>
> +FLAT Instructions
> +------------------
> +These instructions are only present in the Sea Islands and Volcanic Islands
> +instruction set. All FLAT instructions are supported for these architectures
> +
> MUBUF Instructions
> ------------------
> All non-atomic MUBUF instructions are supported.
> diff --git a/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
> index 95025a6..34529d8 100644
> --- a/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
> +++ b/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
> @@ -376,6 +376,10 @@ public:
> OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
> OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
>
> + OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands);
> + OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands);
> + void cvtFlat(MCInst &Inst, const OperandVector &Operands);
> +
> void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
> OperandMatchResultTy parseOffset(OperandVector &Operands);
> OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
> @@ -1092,6 +1096,67 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
> }
>
> //===----------------------------------------------------------------------===//
> +// flat
> +//===----------------------------------------------------------------------===//
> +
> +static const OptionalOperand FlatOptionalOps [] = {
> + {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
> + {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
> + {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
> +};
> +
> +static const OptionalOperand FlatAtomicOptionalOps [] = {
> + {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
> + {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
> +};
> +
> +AMDGPUAsmParser::OperandMatchResultTy
> +AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) {
> + return parseOptionalOps(FlatOptionalOps, Operands);
> +}
> +
> +AMDGPUAsmParser::OperandMatchResultTy
> +AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) {
> + return parseOptionalOps(FlatAtomicOptionalOps, Operands);
> +}
> +
> +void AMDGPUAsmParser::cvtFlat(MCInst &Inst,
> + const OperandVector &Operands) {
> + std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
Don't need enum keyword
> +
> + for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
> + AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
> +
> + // Add the register arguments
> + if (Op.isReg()) {
> + Op.addRegOperands(Inst, 1);
> + continue;
> + }
> +
> + // Handle 'glc' token which is sometimes hard-coded into the
> + // asm string. There are no MCInst operands for these.
> + if (Op.isToken())
> + continue;
> +
> + // Handle optional arguments
> + OptionalIdx[Op.getImmTy()] = i;
> +
> + }
> +
> + // flat atomic instructions don't have a glc argument
Period / capitalize
LGTM
>
> 0004-R600-SI-Add-mcpu-bonaire-to-a-test-that-uses-flat-ad.patch
>
>
> From 8c0ee7558ba24e32d95275d7044f92853e9d7ea2 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 5 Jun 2015 17:01:39 -0400
> Subject: [PATCH 4/5] R600/SI: Add -mcpu=bonaire to a test that uses flat
> address space
>
> Flat instructions don't exist on SI, but there is a bug in the backend that
> allows them to be selected.
> ---
> test/CodeGen/R600/cgp-addressing-modes.ll | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
LGTM
>
>
> 0005-R600-SI-Add-VI-patterns-to-select-FLAT-instructions-.patch
>
>
> From 72a4e6ffae69f9655d116c07a132155d542ee12f Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 5 Jun 2015 21:00:43 -0400
> Subject: [PATCH 5/5] R600/SI: Add VI patterns to select FLAT instructions for
> global memory ops
>
> The MUBUF addr64 bit has been removed on VI, so we must use FLAT
> instructions when the pointer is stored in VGPRs.
> ---
> lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 4 +
> lib/Target/R600/VIInstructions.td | 42 +++++
> test/CodeGen/R600/cgp-addressing-modes.ll | 8 +-
> test/CodeGen/R600/global_atomics.ll | 280 +++++++++++++++++++++---------
> 4 files changed, 252 insertions(+), 82 deletions(-)
>
> diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> index df4461e..2ed0d49 100644
> --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> @@ -1025,6 +1025,10 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
> SDValue &SLC, SDValue &TFE) const {
> SDValue Ptr, Offen, Idxen, Addr64;
>
> + // addr64 bit was removed for volcanic islands.
> + if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
> + return false;
It would also be a good idea to check for VI in isLegalAddressingMode
for global / constant / private to not do the normal mubuf offset
requirements check since flat instructions don't have any useful
addressing modes.
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