[PATCH] [ARM] Be Conservative when coalescing into SP

[Tim Northover]

Hi,

This looks more like a bug with how we model t2SUBri's register usage to me. For example we still allow someone to assemble "sub r12, sp, #80" with this change. Also, the kind of logic you're trying to add here seems to be completely incidental to whether the register is reserved or not: either the register classes model the constraints of the instruction, or they don't.

I'd probably split up the definitions to create something like Thumb's "tSUBspi" and make the normal variants take and define an rGPR.

Also, there should be a test for this.

Cheers.

Tim.


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http://reviews.llvm.org/D10287

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