[llvm] r239105 - [SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN

[Benjamin Kramer]

Author: d0k
Date: Thu Jun  4 17:05:51 2015
New Revision: 239105

URL: http://llvm.org/viewvc/llvm-project?rev=239105&view=rev
Log:
[SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN

The big/small ordering here is based on signed values so SmallValue will
be INT_MIN and BigValue 0. This shouldn't be a problem but the code
assumed that BigValue always had more bits set than SmallValue.

We used to just miss the transformation, but a recent refactoring of
mine turned this into an assertion failure.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/test/CodeGen/X86/switch-or.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=239105&r1=239104&r2=239105&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jun  4 17:05:51 2015
@@ -7807,21 +7807,17 @@ void SelectionDAGBuilder::lowerWorkItem(
       const APInt &BigValue = Big.Low->getValue();
 
       // Check that there is only one bit different.
-      if ((BigValue ^ SmallValue).isPowerOf2()) {
-        // Isolate the common bit.
-        APInt CommonBit = BigValue & ~SmallValue;
-        assert((SmallValue | CommonBit) == BigValue &&
-               CommonBit.countPopulation() == 1 && "Not a common bit?");
-
+      APInt CommonBit = BigValue ^ SmallValue;
+      if (CommonBit.isPowerOf2()) {
         SDValue CondLHS = getValue(Cond);
         EVT VT = CondLHS.getValueType();
         SDLoc DL = getCurSDLoc();
 
         SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
                                  DAG.getConstant(CommonBit, DL, VT));
-        SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
-                                    DAG.getConstant(BigValue, DL, VT),
-                                    ISD::SETEQ);
+        SDValue Cond = DAG.getSetCC(
+            DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
+            ISD::SETEQ);
 
         // Update successor info.
         // Both Small and Big will jump to Small.BB, so we sum up the weights.

Modified: llvm/trunk/test/CodeGen/X86/switch-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-or.ll?rev=239105&r1=239104&r2=239105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/switch-or.ll (original)
+++ llvm/trunk/test/CodeGen/X86/switch-or.ll Thu Jun  4 17:05:51 2015
@@ -1,10 +1,11 @@
 ; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s
 
 ; Check that merging switch cases that differ in one bit works.
+; CHECK-LABEL: test1
 ; CHECK: orl $2
 ; CHECK-NEXT: cmpl $6
 
-define void @foo(i32 %variable) nounwind {
+define void @test1(i32 %variable) nounwind {
 entry:
   switch i32 %variable, label %if.end [
     i32 4, label %if.then
@@ -12,6 +13,24 @@ entry:
   ]
 
 if.then:
+  %call = tail call i32 (...) @bar() nounwind
+  ret void
+
+if.end:
+  ret void
+}
+
+; CHECK-LABEL: test2
+; CHECK: orl $-2147483648
+; CHECK-NEXT: cmpl $-2147483648
+define void @test2(i32 %variable) nounwind {
+entry:
+  switch i32 %variable, label %if.end [
+    i32 0, label %if.then
+    i32 -2147483648, label %if.then
+  ]
+
+if.then:
   %call = tail call i32 (...) @bar() nounwind
   ret void