[llvm] r238858 - AArch64: fix typo in SMIN far atomics and add tests
Tim Northover
tnorthover at apple.com
Tue Jun 2 11:37:20 PDT 2015
Author: tnorthover
Date: Tue Jun 2 13:37:20 2015
New Revision: 238858
URL: http://llvm.org/viewvc/llvm-project?rev=238858&view=rev
Log:
AArch64: fix typo in SMIN far atomics and add tests
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/test/MC/AArch64/armv8.1a-atomic.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-atomic.txt
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=238858&r1=238857&r2=238858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Jun 2 13:37:20 2015
@@ -789,7 +789,7 @@ defm LDSMAXA : LDOPregister<0b100, "sma
defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
-defm LDSMIN : LDOPregister<0b101, "smin`", 0, 0, "">;
+defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
Modified: llvm/trunk/test/MC/AArch64/armv8.1a-atomic.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.1a-atomic.s?rev=238858&r1=238857&r2=238858&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.1a-atomic.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.1a-atomic.s Tue Jun 2 13:37:20 2015
@@ -84,6 +84,7 @@
ldsminlb w0, w1, [x2]
ldumaxalh w0, w1, [x2]
ldumin w0, w1, [x2]
+ ldsminb w2, w3, [x5]
//CHECK: ldadda x0, x1, [x2] // encoding: [0x41,0x00,0xa0,0xf8]
//CHECK: ldclrl x0, x1, [x2] // encoding: [0x41,0x10,0x60,0xf8]
//CHECK: ldeoral x0, x1, [x2] // encoding: [0x41,0x20,0xe0,0xf8]
@@ -92,6 +93,7 @@
//CHECK: ldsminlb w0, w1, [x2] // encoding: [0x41,0x50,0x60,0x38]
//CHECK: ldumaxalh w0, w1, [x2] // encoding: [0x41,0x60,0xe0,0x78]
//CHECK: ldumin w0, w1, [x2] // encoding: [0x41,0x70,0x20,0xb8]
+//CHECK: ldsminb w2, w3, [x5] // encoding: [0xa3,0x50,0x22,0x38]
// ST<OP> intructions: aliases to LD<OP>
stADDlb w0, [x2]
@@ -102,6 +104,7 @@
stsminh w0, [x2]
stumax w0, [x2]
stumin x0, [x2]
+ stsminl x29, [sp]
//CHECK: staddlb w0, [x2] // encoding: [0x5f,0x00,0x60,0x38]
//CHECK: stclrlh w0, [x2] // encoding: [0x5f,0x10,0x60,0x78]
//CHECK: steorl w0, [x2] // encoding: [0x5f,0x20,0x60,0xb8]
@@ -110,6 +113,8 @@
//CHECK: stsminh w0, [x2] // encoding: [0x5f,0x50,0x20,0x78]
//CHECK: stumax w0, [x2] // encoding: [0x5f,0x60,0x20,0xb8]
//CHECK: stumin x0, [x2] // encoding: [0x5f,0x70,0x20,0xf8]
+//CHECK: stsminl x29, [sp] // encoding: [0xff,0x53,0x7d,0xf8]
+
ldsmax x0, x1, [w2]
ldeorl w0, w1, [w2]
Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-atomic.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-atomic.txt?rev=238858&r1=238857&r2=238858&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-atomic.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-atomic.txt Tue Jun 2 13:37:20 2015
@@ -51,6 +51,7 @@
0x41,0x50,0x60,0x38
0x41,0x60,0xe0,0x78
0x41,0x70,0x20,0xb8
+0xab,0x51,0xe7,0x78
# CHECK: ldadda x0, x1, [x2]
# CHECK: ldclrl x0, x1, [x2]
# CHECK: ldeoral x0, x1, [x2]
@@ -59,6 +60,7 @@
# CHECK: ldsminlb w0, w1, [x2]
# CHECK: ldumaxalh w0, w1, [x2]
# CHECK: ldumin w0, w1, [x2]
+# CHECK: ldsminalh w7, w11, [x13]
0x5f,0x00,0x60,0x38
0x5f,0x10,0x60,0x78
@@ -68,6 +70,7 @@
0x5f,0x50,0x20,0x78
0x5f,0x60,0x20,0xb8
0x5f,0x70,0x20,0xf8
+0xff,0x53,0x7d,0xf8
# CHECK: staddlb w0, [x2]
# CHECK: stclrlh w0, [x2]
# CHECK: steorl w0, [x2]
@@ -76,6 +79,7 @@
# CHECK: stsminh w0, [x2]
# CHECK: stumax w0, [x2]
# CHECK: stumin x0, [x2]
+# CHECK: stsminl x29, [sp]
0x82,0x7c,0x20,0x48
0x82,0x7c,0x20,0x08
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