[llvm] r238811 - AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
Elena Demikhovsky
elena.demikhovsky at intel.com
Tue Jun 2 01:28:57 PDT 2015
Author: delena
Date: Tue Jun 2 03:28:57 2015
New Revision: 238811
URL: http://llvm.org/viewvc/llvm-project?rev=238811&view=rev
Log:
AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger at intel.com)
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/MC/X86/avx512-encodings.s
llvm/trunk/test/MC/X86/intel-syntax-avx512.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=238811&r1=238810&r2=238811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Jun 2 03:28:57 2015
@@ -5996,6 +5996,38 @@ multiclass avx512_fp_packed_imm<bits<8>
}
}
+//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
+// op(reg_vec2,mem_scalar,imm)
+//all instruction created with FROUND_CURRENT
+multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ X86VectorVTInfo _> {
+
+ defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
+ (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
+ OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (OpNode (_.VT _.RC:$src1),
+ (_.VT _.RC:$src2),
+ (i8 imm:$src3),
+ (i32 FROUND_CURRENT))>;
+ let mayLoad = 1 in {
+ defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
+ (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
+ OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (OpNode (_.VT _.RC:$src1),
+ (_.VT (scalar_to_vector
+ (_.ScalarLdFrag addr:$src2))),
+ (i8 imm:$src3),
+ (i32 FROUND_CURRENT))>;
+
+ let isAsmParserOnly = 1 in {
+ defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
+ (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
+ OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ []>;
+ }
+ }
+}
+
//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
SDNode OpNode, X86VectorVTInfo _>{
@@ -6008,6 +6040,11 @@ multiclass avx512_fp_sae_packed_imm<bits
(i8 imm:$src3),
(i32 FROUND_NO_EXC))>, EVEX_B;
}
+//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
+multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
+ SDNode OpNode, X86VectorVTInfo _> {
+ defm NAME: avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _>;
+}
multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
@@ -6025,6 +6062,14 @@ multiclass avx512_common_fp_sae_packed_i
}
}
+multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
+ X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
+ let Predicates = [prd] in {
+ defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
+ avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
+ }
+}
+
defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
@@ -6032,6 +6077,12 @@ defm VFIXUPIMMPS : avx512_common_fp_sae_
avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
+defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
+ 0x55, X86VFixupimm, HasAVX512>,
+ AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
+defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
+ 0x55, X86VFixupimm, HasAVX512>,
+ AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
0x50, X86VRange, HasDQI>,
@@ -6040,17 +6091,3 @@ defm VRANGEPS : avx512_common_fp_sae_pac
0x50, X86VRange, HasDQI>,
AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Modified: llvm/trunk/test/MC/X86/avx512-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=238811&r1=238810&r2=238811&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/avx512-encodings.s (original)
+++ llvm/trunk/test/MC/X86/avx512-encodings.s Tue Jun 2 03:28:57 2015
@@ -7860,6 +7860,102 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
// CHECK: encoding: [0x62,0x73,0xd5,0x50,0x54,0x8a,0xf8,0xfb,0xff,0xff,0x7b]
vfixupimmpd $0x7b, -1032(%rdx){1to8}, %zmm21, %zmm9
+// CHECK: vfixupimmss $171, %xmm28, %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x13,0x6d,0x00,0x55,0xfc,0xab]
+ vfixupimmss $0xab, %xmm28, %xmm18, %xmm15
+
+// CHECK: vfixupimmss $171, %xmm28, %xmm18, %xmm15 {%k5}
+// CHECK: encoding: [0x62,0x13,0x6d,0x05,0x55,0xfc,0xab]
+ vfixupimmss $0xab, %xmm28, %xmm18, %xmm15 {%k5}
+
+// CHECK: vfixupimmss $171, %xmm28, %xmm18, %xmm15 {%k5} {z}
+// CHECK: encoding: [0x62,0x13,0x6d,0x85,0x55,0xfc,0xab]
+ vfixupimmss $0xab, %xmm28, %xmm18, %xmm15 {%k5} {z}
+
+// CHECK: vfixupimmss $171,{sae}, %xmm28, %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x13,0x6d,0x10,0x55,0xfc,0xab]
+ vfixupimmss $0xab,{sae}, %xmm28, %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, %xmm28, %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x13,0x6d,0x00,0x55,0xfc,0x7b]
+ vfixupimmss $0x7b, %xmm28, %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123,{sae}, %xmm28, %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x13,0x6d,0x10,0x55,0xfc,0x7b]
+ vfixupimmss $0x7b,{sae}, %xmm28, %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, (%rcx), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x39,0x7b]
+ vfixupimmss $0x7b, (%rcx), %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, 291(%rax,%r14,8), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x33,0x6d,0x00,0x55,0xbc,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfixupimmss $0x7b, 291(%rax,%r14,8), %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, 508(%rdx), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x7a,0x7f,0x7b]
+ vfixupimmss $0x7b, 508(%rdx), %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, 512(%rdx), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0xba,0x00,0x02,0x00,0x00,0x7b]
+ vfixupimmss $0x7b, 512(%rdx), %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, -512(%rdx), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x7a,0x80,0x7b]
+ vfixupimmss $0x7b, -512(%rdx), %xmm18, %xmm15
+
+// CHECK: vfixupimmss $123, -516(%rdx), %xmm18, %xmm15
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0xba,0xfc,0xfd,0xff,0xff,0x7b]
+ vfixupimmss $0x7b, -516(%rdx), %xmm18, %xmm15
+
+// CHECK: vfixupimmsd $171, %xmm5, %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xed,0xab]
+ vfixupimmsd $0xab, %xmm5, %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $171, %xmm5, %xmm26, %xmm13 {%k6}
+// CHECK: encoding: [0x62,0x73,0xad,0x06,0x55,0xed,0xab]
+ vfixupimmsd $0xab, %xmm5, %xmm26, %xmm13 {%k6}
+
+// CHECK: vfixupimmsd $171, %xmm5, %xmm26, %xmm13 {%k6} {z}
+// CHECK: encoding: [0x62,0x73,0xad,0x86,0x55,0xed,0xab]
+ vfixupimmsd $0xab, %xmm5, %xmm26, %xmm13 {%k6} {z}
+
+// CHECK: vfixupimmsd $171,{sae}, %xmm5, %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x10,0x55,0xed,0xab]
+ vfixupimmsd $0xab,{sae}, %xmm5, %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, %xmm5, %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xed,0x7b]
+ vfixupimmsd $0x7b, %xmm5, %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123,{sae}, %xmm5, %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x10,0x55,0xed,0x7b]
+ vfixupimmsd $0x7b,{sae}, %xmm5, %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, (%rcx), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x29,0x7b]
+ vfixupimmsd $0x7b, (%rcx), %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, 291(%rax,%r14,8), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x33,0xad,0x00,0x55,0xac,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfixupimmsd $0x7b, 291(%rax,%r14,8), %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, 1016(%rdx), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x6a,0x7f,0x7b]
+ vfixupimmsd $0x7b, 1016(%rdx), %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, 1024(%rdx), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0x00,0x04,0x00,0x00,0x7b]
+ vfixupimmsd $0x7b, 1024(%rdx), %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, -1024(%rdx), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x6a,0x80,0x7b]
+ vfixupimmsd $0x7b, -1024(%rdx), %xmm26, %xmm13
+
+// CHECK: vfixupimmsd $123, -1032(%rdx), %xmm26, %xmm13
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0xf8,0xfb,0xff,0xff,0x7b]
+ vfixupimmsd $0x7b, -1032(%rdx), %xmm26, %xmm13
+
// CHECK: vpshufd $171, %zmm25, %zmm19
// CHECK: encoding: [0x62,0x81,0x7d,0x48,0x70,0xd9,0xab]
vpshufd $171, %zmm25, %zmm19
Modified: llvm/trunk/test/MC/X86/intel-syntax-avx512.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-avx512.s?rev=238811&r1=238810&r2=238811&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-avx512.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax-avx512.s Tue Jun 2 03:28:57 2015
@@ -161,15 +161,98 @@ vaddpd zmm1,zmm1,zmm2,{rz-sae}
vcmpps k2,zmm17,DWORD PTR [rdx-0x204]{1to16},0x7b
-
-
-
-
-
-
-
-
-
-
-
-
+// CHECK: vfixupimmss xmm15 , xmm18, xmm28, 171
+// CHECK: encoding: [0x62,0x13,0x6d,0x00,0x55,0xfc,0xab]
+ vfixupimmss xmm15,xmm18,xmm28,0xab
+
+// CHECK: vfixupimmss xmm15 {k5}, xmm18, xmm28, 171
+// CHECK: encoding: [0x62,0x13,0x6d,0x05,0x55,0xfc,0xab]
+ vfixupimmss xmm15{k5},xmm18,xmm28,0xab
+
+// CHECK: vfixupimmss xmm15 {k5} {z}, xmm18, xmm28, 171
+// CHECK: encoding: [0x62,0x13,0x6d,0x85,0x55,0xfc,0xab]
+ vfixupimmss xmm15{k5} {z},xmm18,xmm28,0xab
+
+// CHECK: vfixupimmss xmm15 , xmm18, xmm28,{sae}, 171
+// CHECK: encoding: [0x62,0x13,0x6d,0x10,0x55,0xfc,0xab]
+ vfixupimmss xmm15,xmm18,xmm28,{sae},0xab
+
+// CHECK: vfixupimmss xmm15 , xmm18, xmm28, 123
+// CHECK: encoding: [0x62,0x13,0x6d,0x00,0x55,0xfc,0x7b]
+ vfixupimmss xmm15,xmm18,xmm28,0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, xmm28,{sae}, 123
+// CHECK: encoding: [0x62,0x13,0x6d,0x10,0x55,0xfc,0x7b]
+ vfixupimmss xmm15,xmm18,xmm28,{sae},0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rcx], 123
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x39,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rcx],0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rax + 8*r14 + 291], 123
+// CHECK: encoding: [0x62,0x33,0x6d,0x00,0x55,0xbc,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rdx + 508], 123
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x7a,0x7f,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rdx+0x1fc],0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rdx + 512], 123
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0xba,0x00,0x02,0x00,0x00,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rdx+0x200],0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rdx - 512], 123
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0x7a,0x80,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rdx-0x200],0x7b
+
+// CHECK: vfixupimmss xmm15 , xmm18, dword ptr [rdx - 516], 123
+// CHECK: encoding: [0x62,0x73,0x6d,0x00,0x55,0xba,0xfc,0xfd,0xff,0xff,0x7b]
+ vfixupimmss xmm15,xmm18,DWORD PTR [rdx-0x204],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, xmm5, 171
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xed,0xab]
+ vfixupimmsd xmm13,xmm26,xmm5,0xab
+
+// CHECK: vfixupimmsd xmm13 {k6}, xmm26, xmm5, 171
+// CHECK: encoding: [0x62,0x73,0xad,0x06,0x55,0xed,0xab]
+ vfixupimmsd xmm13{k6},xmm26,xmm5,0xab
+
+// CHECK: vfixupimmsd xmm13 {k6} {z}, xmm26, xmm5, 171
+// CHECK: encoding: [0x62,0x73,0xad,0x86,0x55,0xed,0xab]
+ vfixupimmsd xmm13{k6} {z},xmm26,xmm5,0xab
+
+// CHECK: vfixupimmsd xmm13 , xmm26, xmm5,{sae}, 171
+// CHECK: encoding: [0x62,0x73,0xad,0x10,0x55,0xed,0xab]
+ vfixupimmsd xmm13,xmm26,xmm5,{sae},0xab
+
+// CHECK: vfixupimmsd xmm13 , xmm26, xmm5, 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xed,0x7b]
+ vfixupimmsd xmm13,xmm26,xmm5,0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, xmm5,{sae}, 123
+// CHECK: encoding: [0x62,0x73,0xad,0x10,0x55,0xed,0x7b]
+ vfixupimmsd xmm13,xmm26,xmm5,{sae},0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rcx], 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x29,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rcx],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rax + 8*r14 + 291], 123
+// CHECK: encoding: [0x62,0x33,0xad,0x00,0x55,0xac,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rax+r14*8+0x123],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx + 1016], 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x6a,0x7f,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rdx+0x3f8],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx + 1024], 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0x00,0x04,0x00,0x00,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rdx+0x400],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx - 1024], 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0x6a,0x80,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rdx-0x400],0x7b
+
+// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx - 1032], 123
+// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0xf8,0xfb,0xff,0xff,0x7b]
+ vfixupimmsd xmm13,xmm26,QWORD PTR [rdx-0x408],0x7b
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