[llvm] r238748 - [Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath.
Colin LeMahieu
colinl at codeaurora.org
Mon Jun 1 12:40:39 PDT 2015
Ok, that'll probably make the hexagon-clang bot fail a test which I un-xfailed.
-----Original Message-----
From: Rafael Espíndola [mailto:rafael.espindola at gmail.com]
Sent: Monday, June 01, 2015 2:26 PM
To: Colin LeMahieu
Cc: llvm-commits
Subject: Re: [llvm] r238748 - [Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath.
This broke a bot and I reverted it:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio
Cheers,
Rafael
On 1 June 2015 at 10:51, Colin LeMahieu <colinl at codeaurora.org> wrote:
> Author: colinl
> Date: Mon Jun 1 09:51:26 2015
> New Revision: 238748
>
> URL: http://llvm.org/viewvc/llvm-project?rev=238748&view=rev
> Log:
> [Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath.
>
> Added:
> llvm/trunk/test/CodeGen/Hexagon/relax.ll
> Modified:
> llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
>
> Modified: llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/EL
> FRelocs/Hexagon.def?rev=238748&r1=238747&r2=238748&view=diff
> ======================================================================
> ========
> --- llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def (original)
> +++ llvm/trunk/include/llvm/Support/ELFRelocs/Hexagon.def Mon Jun 1
> +++ 09:51:26 2015
> @@ -90,3 +90,11 @@ ELF_RELOC(R_HEX_IE_GOT_11_X, 82)
> ELF_RELOC(R_HEX_TPREL_32_6_X, 83)
> ELF_RELOC(R_HEX_TPREL_16_X, 84)
> ELF_RELOC(R_HEX_TPREL_11_X, 85)
> +ELF_RELOC(R_HEX_LD_PLT_B22_PCREL, 86)
> +ELF_RELOC(R_HEX_LD_GOT_LO16, 87)
> +ELF_RELOC(R_HEX_LD_GOT_HI16, 88)
> +ELF_RELOC(R_HEX_LD_GOT_32, 89)
> +ELF_RELOC(R_HEX_LD_GOT_16, 90)
> +ELF_RELOC(R_HEX_LD_GOT_32_6_X, 91)
> +ELF_RELOC(R_HEX_LD_GOT_16_X, 92)
> +ELF_RELOC(R_HEX_LD_GOT_11_X, 93)
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTa
> rgetDesc/HexagonAsmBackend.cpp?rev=238748&r1=238747&r2=238748&view=dif
> f
> ======================================================================
> ========
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> +++ Mon Jun 1 09:51:26 2015
> @@ -15,6 +15,8 @@
> #include "llvm/MC/MCAsmBackend.h"
> #include "llvm/MC/MCAssembler.h"
> #include "llvm/MC/MCELFObjectWriter.h"
> +#include "llvm/MC/MCFixupKindInfo.h"
> +#include "llvm/Support/TargetRegistry.h"
>
> using namespace llvm;
> using namespace Hexagon;
> @@ -22,14 +24,132 @@ using namespace Hexagon; namespace {
>
> class HexagonAsmBackend : public MCAsmBackend {
> + uint8_t OSABI;
> + StringRef CPU;
> mutable uint64_t relaxedCnt;
> std::unique_ptr <MCInstrInfo> MCII;
> std::unique_ptr <MCInst *> RelaxTarget;
> public:
> - HexagonAsmBackend(Target const & /*T*/) :
> - MCII (createHexagonMCInstrInfo()), RelaxTarget(new MCInst *){}
> + HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
> + MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){}
> +
> + MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
> + return createHexagonELFObjectWriter(OS, OSABI, CPU); }
>
> - unsigned getNumFixupKinds() const override { return 0; }
> + unsigned getNumFixupKinds() const override {
> + return Hexagon::NumTargetFixupKinds; }
> +
> + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
> + const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
> + // This table *must* be in same the order of fixup_* kinds in
> + // HexagonFixupKinds.h.
> + //
> + // namei offset bits flags
> + {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_LO16", 0, 32, 0},
> + {"fixup_Hexagon_HI16", 0, 32, 0},
> + {"fixup_Hexagon_32", 0, 32, 0},
> + {"fixup_Hexagon_16", 0, 32, 0},
> + {"fixup_Hexagon_8", 0, 32, 0},
> + {"fixup_Hexagon_GPREL16_0", 0, 32, 0},
> + {"fixup_Hexagon_GPREL16_1", 0, 32, 0},
> + {"fixup_Hexagon_GPREL16_2", 0, 32, 0},
> + {"fixup_Hexagon_GPREL16_3", 0, 32, 0},
> + {"fixup_Hexagon_HL16", 0, 32, 0},
> + {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_16_X", 0, 32, 0},
> + {"fixup_Hexagon_12_X", 0, 32, 0},
> + {"fixup_Hexagon_11_X", 0, 32, 0},
> + {"fixup_Hexagon_10_X", 0, 32, 0},
> + {"fixup_Hexagon_9_X", 0, 32, 0},
> + {"fixup_Hexagon_8_X", 0, 32, 0},
> + {"fixup_Hexagon_7_X", 0, 32, 0},
> + {"fixup_Hexagon_6_X", 0, 32, 0},
> + {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_COPY", 0, 32, 0},
> + {"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
> + {"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
> + {"fixup_Hexagon_RELATIVE", 0, 32, 0},
> + {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
> + {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
> + {"fixup_Hexagon_GOTREL_32", 0, 32, 0},
> + {"fixup_Hexagon_GOT_LO16", 0, 32, 0},
> + {"fixup_Hexagon_GOT_HI16", 0, 32, 0},
> + {"fixup_Hexagon_GOT_32", 0, 32, 0},
> + {"fixup_Hexagon_GOT_16", 0, 32, 0},
> + {"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_32", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_16", 0, 32, 0},
> + {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
> + {"fixup_Hexagon_IE_LO16", 0, 32, 0},
> + {"fixup_Hexagon_IE_HI16", 0, 32, 0},
> + {"fixup_Hexagon_IE_32", 0, 32, 0},
> + {"fixup_Hexagon_IE_16", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_32", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_16", 0, 32, 0},
> + {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
> + {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
> + {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
> + {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_GOT_16_X", 0, 32, 0},
> + {"fixup_Hexagon_GOT_11_X", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
> + {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
> + {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
> + {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
> + {"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_IE_16_X", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
> + {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
> + {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
> +
> + if (Kind < FirstTargetFixupKind) {
> + return MCAsmBackend::getFixupKindInfo(Kind);
> + }
> +
> + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
> + "Invalid kind!");
> + return Infos[Kind - FirstTargetFixupKind]; }
>
> void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
> unsigned /*DataSize*/, uint64_t /*Value*/, @@
> -164,26 +284,11 @@ public:
> };
> } // end anonymous namespace
>
> -namespace {
> -class ELFHexagonAsmBackend : public HexagonAsmBackend {
> - uint8_t OSABI;
> -
> -public:
> - ELFHexagonAsmBackend(Target const &T, uint8_t OSABI)
> - : HexagonAsmBackend(T), OSABI(OSABI) {}
> -
> - MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
> - StringRef CPU("HexagonV4");
> - return createHexagonELFObjectWriter(OS, OSABI, CPU);
> - }
> -};
> -} // end anonymous namespace
> -
> namespace llvm {
> MCAsmBackend *createHexagonAsmBackend(Target const &T,
> MCRegisterInfo const & /*MRI*/,
> - StringRef TT, StringRef /*CPU*/) {
> + StringRef TT, StringRef CPU) {
> uint8_t OSABI =
> MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
> - return new ELFHexagonAsmBackend(T, OSABI);
> + return new HexagonAsmBackend(T, OSABI, CPU);
> }
> }
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTa
> rgetDesc/HexagonELFObjectWriter.cpp?rev=238748&r1=238747&r2=238748&vie
> w=diff
> ======================================================================
> ========
> ---
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.
> +++ cpp Mon Jun 1 09:51:26 2015
> @@ -8,6 +8,7 @@
>
> //===-----------------------------------------------------------------
> -----===//
>
> #include "Hexagon.h"
> +#include "MCTargetDesc/HexagonFixupKinds.h"
> #include "llvm/MC/MCAssembler.h"
> #include "llvm/MC/MCELFObjectWriter.h"
> #include "llvm/Support/Debug.h"
> @@ -40,17 +41,306 @@ HexagonELFObjectWriter::HexagonELFObject
> unsigned HexagonELFObjectWriter::GetRelocType(MCValue const &/*Target*/,
> MCFixup const &Fixup,
> bool IsPCRel) const {
> + // determine the type of the relocation
> unsigned Type = (unsigned)ELF::R_HEX_NONE;
> - llvm::MCFixupKind Kind = Fixup.getKind();
> + unsigned Kind = (unsigned)Fixup.getKind();
>
> switch (Kind) {
> - default:
> - DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
> - llvm_unreachable("Unimplemented Fixup kind!");
> - break;
> - case FK_Data_4:
> - Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
> - break;
> + default:
> + DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
> + llvm_unreachable("Unimplemented Fixup kind!");
> + break;
> + case FK_Data_4:
> + Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
> + break;
> + case FK_PCRel_4:
> + Type = ELF::R_HEX_32_PCREL;
> + break;
> + case FK_Data_2:
> + Type = ELF::R_HEX_16;
> + break;
> + case FK_Data_1:
> + Type = ELF::R_HEX_8;
> + break;
> + case fixup_Hexagon_B22_PCREL:
> + Type = ELF::R_HEX_B22_PCREL;
> + break;
> + case fixup_Hexagon_B15_PCREL:
> + Type = ELF::R_HEX_B15_PCREL;
> + break;
> + case fixup_Hexagon_B7_PCREL:
> + Type = ELF::R_HEX_B7_PCREL;
> + break;
> + case fixup_Hexagon_LO16:
> + Type = ELF::R_HEX_LO16;
> + break;
> + case fixup_Hexagon_HI16:
> + Type = ELF::R_HEX_HI16;
> + break;
> + case fixup_Hexagon_32:
> + Type = ELF::R_HEX_32;
> + break;
> + case fixup_Hexagon_16:
> + Type = ELF::R_HEX_16;
> + break;
> + case fixup_Hexagon_8:
> + Type = ELF::R_HEX_8;
> + break;
> + case fixup_Hexagon_GPREL16_0:
> + Type = ELF::R_HEX_GPREL16_0;
> + break;
> + case fixup_Hexagon_GPREL16_1:
> + Type = ELF::R_HEX_GPREL16_1;
> + break;
> + case fixup_Hexagon_GPREL16_2:
> + Type = ELF::R_HEX_GPREL16_2;
> + break;
> + case fixup_Hexagon_GPREL16_3:
> + Type = ELF::R_HEX_GPREL16_3;
> + break;
> + case fixup_Hexagon_HL16:
> + Type = ELF::R_HEX_HL16;
> + break;
> + case fixup_Hexagon_B13_PCREL:
> + Type = ELF::R_HEX_B13_PCREL;
> + break;
> + case fixup_Hexagon_B9_PCREL:
> + Type = ELF::R_HEX_B9_PCREL;
> + break;
> + case fixup_Hexagon_B32_PCREL_X:
> + Type = ELF::R_HEX_B32_PCREL_X;
> + break;
> + case fixup_Hexagon_32_6_X:
> + Type = ELF::R_HEX_32_6_X;
> + break;
> + case fixup_Hexagon_B22_PCREL_X:
> + Type = ELF::R_HEX_B22_PCREL_X;
> + break;
> + case fixup_Hexagon_B15_PCREL_X:
> + Type = ELF::R_HEX_B15_PCREL_X;
> + break;
> + case fixup_Hexagon_B13_PCREL_X:
> + Type = ELF::R_HEX_B13_PCREL_X;
> + break;
> + case fixup_Hexagon_B9_PCREL_X:
> + Type = ELF::R_HEX_B9_PCREL_X;
> + break;
> + case fixup_Hexagon_B7_PCREL_X:
> + Type = ELF::R_HEX_B7_PCREL_X;
> + break;
> + case fixup_Hexagon_16_X:
> + Type = ELF::R_HEX_16_X;
> + break;
> + case fixup_Hexagon_12_X:
> + Type = ELF::R_HEX_12_X;
> + break;
> + case fixup_Hexagon_11_X:
> + Type = ELF::R_HEX_11_X;
> + break;
> + case fixup_Hexagon_10_X:
> + Type = ELF::R_HEX_10_X;
> + break;
> + case fixup_Hexagon_9_X:
> + Type = ELF::R_HEX_9_X;
> + break;
> + case fixup_Hexagon_8_X:
> + Type = ELF::R_HEX_8_X;
> + break;
> + case fixup_Hexagon_7_X:
> + Type = ELF::R_HEX_7_X;
> + break;
> + case fixup_Hexagon_6_X:
> + Type = ELF::R_HEX_6_X;
> + break;
> + case fixup_Hexagon_32_PCREL:
> + Type = ELF::R_HEX_32_PCREL;
> + break;
> + case fixup_Hexagon_COPY:
> + Type = ELF::R_HEX_COPY;
> + break;
> + case fixup_Hexagon_GLOB_DAT:
> + Type = ELF::R_HEX_GLOB_DAT;
> + break;
> + case fixup_Hexagon_JMP_SLOT:
> + Type = ELF::R_HEX_JMP_SLOT;
> + break;
> + case fixup_Hexagon_RELATIVE:
> + Type = ELF::R_HEX_RELATIVE;
> + break;
> + case fixup_Hexagon_PLT_B22_PCREL:
> + Type = ELF::R_HEX_PLT_B22_PCREL;
> + break;
> + case fixup_Hexagon_GOTREL_LO16:
> + Type = ELF::R_HEX_GOTREL_LO16;
> + break;
> + case fixup_Hexagon_GOTREL_HI16:
> + Type = ELF::R_HEX_GOTREL_HI16;
> + break;
> + case fixup_Hexagon_GOTREL_32:
> + Type = ELF::R_HEX_GOTREL_32;
> + break;
> + case fixup_Hexagon_GOT_LO16:
> + Type = ELF::R_HEX_GOT_LO16;
> + break;
> + case fixup_Hexagon_GOT_HI16:
> + Type = ELF::R_HEX_GOT_HI16;
> + break;
> + case fixup_Hexagon_GOT_32:
> + Type = ELF::R_HEX_GOT_32;
> + break;
> + case fixup_Hexagon_GOT_16:
> + Type = ELF::R_HEX_GOT_16;
> + break;
> + case fixup_Hexagon_DTPMOD_32:
> + Type = ELF::R_HEX_DTPMOD_32;
> + break;
> + case fixup_Hexagon_DTPREL_LO16:
> + Type = ELF::R_HEX_DTPREL_LO16;
> + break;
> + case fixup_Hexagon_DTPREL_HI16:
> + Type = ELF::R_HEX_DTPREL_HI16;
> + break;
> + case fixup_Hexagon_DTPREL_32:
> + Type = ELF::R_HEX_DTPREL_32;
> + break;
> + case fixup_Hexagon_DTPREL_16:
> + Type = ELF::R_HEX_DTPREL_16;
> + break;
> + case fixup_Hexagon_GD_PLT_B22_PCREL:
> + Type = ELF::R_HEX_GD_PLT_B22_PCREL;
> + break;
> + case fixup_Hexagon_LD_PLT_B22_PCREL:
> + Type = ELF::R_HEX_LD_PLT_B22_PCREL;
> + break;
> + case fixup_Hexagon_GD_GOT_LO16:
> + Type = ELF::R_HEX_GD_GOT_LO16;
> + break;
> + case fixup_Hexagon_GD_GOT_HI16:
> + Type = ELF::R_HEX_GD_GOT_HI16;
> + break;
> + case fixup_Hexagon_GD_GOT_32:
> + Type = ELF::R_HEX_GD_GOT_32;
> + break;
> + case fixup_Hexagon_GD_GOT_16:
> + Type = ELF::R_HEX_GD_GOT_16;
> + break;
> + case fixup_Hexagon_LD_GOT_LO16:
> + Type = ELF::R_HEX_LD_GOT_LO16;
> + break;
> + case fixup_Hexagon_LD_GOT_HI16:
> + Type = ELF::R_HEX_LD_GOT_HI16;
> + break;
> + case fixup_Hexagon_LD_GOT_32:
> + Type = ELF::R_HEX_LD_GOT_32;
> + break;
> + case fixup_Hexagon_LD_GOT_16:
> + Type = ELF::R_HEX_LD_GOT_16;
> + break;
> + case fixup_Hexagon_IE_LO16:
> + Type = ELF::R_HEX_IE_LO16;
> + break;
> + case fixup_Hexagon_IE_HI16:
> + Type = ELF::R_HEX_IE_HI16;
> + break;
> + case fixup_Hexagon_IE_32:
> + Type = ELF::R_HEX_IE_32;
> + break;
> + case fixup_Hexagon_IE_GOT_LO16:
> + Type = ELF::R_HEX_IE_GOT_LO16;
> + break;
> + case fixup_Hexagon_IE_GOT_HI16:
> + Type = ELF::R_HEX_IE_GOT_HI16;
> + break;
> + case fixup_Hexagon_IE_GOT_32:
> + Type = ELF::R_HEX_IE_GOT_32;
> + break;
> + case fixup_Hexagon_IE_GOT_16:
> + Type = ELF::R_HEX_IE_GOT_16;
> + break;
> + case fixup_Hexagon_TPREL_LO16:
> + Type = ELF::R_HEX_TPREL_LO16;
> + break;
> + case fixup_Hexagon_TPREL_HI16:
> + Type = ELF::R_HEX_TPREL_HI16;
> + break;
> + case fixup_Hexagon_TPREL_32:
> + Type = ELF::R_HEX_TPREL_32;
> + break;
> + case fixup_Hexagon_TPREL_16:
> + Type = ELF::R_HEX_TPREL_16;
> + break;
> + case fixup_Hexagon_6_PCREL_X:
> + Type = ELF::R_HEX_6_PCREL_X;
> + break;
> + case fixup_Hexagon_GOTREL_32_6_X:
> + Type = ELF::R_HEX_GOTREL_32_6_X;
> + break;
> + case fixup_Hexagon_GOTREL_16_X:
> + Type = ELF::R_HEX_GOTREL_16_X;
> + break;
> + case fixup_Hexagon_GOTREL_11_X:
> + Type = ELF::R_HEX_GOTREL_11_X;
> + break;
> + case fixup_Hexagon_GOT_32_6_X:
> + Type = ELF::R_HEX_GOT_32_6_X;
> + break;
> + case fixup_Hexagon_GOT_16_X:
> + Type = ELF::R_HEX_GOT_16_X;
> + break;
> + case fixup_Hexagon_GOT_11_X:
> + Type = ELF::R_HEX_GOT_11_X;
> + break;
> + case fixup_Hexagon_DTPREL_32_6_X:
> + Type = ELF::R_HEX_DTPREL_32_6_X;
> + break;
> + case fixup_Hexagon_DTPREL_16_X:
> + Type = ELF::R_HEX_DTPREL_16_X;
> + break;
> + case fixup_Hexagon_DTPREL_11_X:
> + Type = ELF::R_HEX_DTPREL_11_X;
> + break;
> + case fixup_Hexagon_GD_GOT_32_6_X:
> + Type = ELF::R_HEX_GD_GOT_32_6_X;
> + break;
> + case fixup_Hexagon_GD_GOT_16_X:
> + Type = ELF::R_HEX_GD_GOT_16_X;
> + break;
> + case fixup_Hexagon_GD_GOT_11_X:
> + Type = ELF::R_HEX_GD_GOT_11_X;
> + break;
> + case fixup_Hexagon_LD_GOT_32_6_X:
> + Type = ELF::R_HEX_LD_GOT_32_6_X;
> + break;
> + case fixup_Hexagon_LD_GOT_16_X:
> + Type = ELF::R_HEX_LD_GOT_16_X;
> + break;
> + case fixup_Hexagon_LD_GOT_11_X:
> + Type = ELF::R_HEX_LD_GOT_11_X;
> + break;
> + case fixup_Hexagon_IE_32_6_X:
> + Type = ELF::R_HEX_IE_32_6_X;
> + break;
> + case fixup_Hexagon_IE_16_X:
> + Type = ELF::R_HEX_IE_16_X;
> + break;
> + case fixup_Hexagon_IE_GOT_32_6_X:
> + Type = ELF::R_HEX_IE_GOT_32_6_X;
> + break;
> + case fixup_Hexagon_IE_GOT_16_X:
> + Type = ELF::R_HEX_IE_GOT_16_X;
> + break;
> + case fixup_Hexagon_IE_GOT_11_X:
> + Type = ELF::R_HEX_IE_GOT_11_X;
> + break;
> + case fixup_Hexagon_TPREL_32_6_X:
> + Type = ELF::R_HEX_TPREL_32_6_X;
> + break;
> + case fixup_Hexagon_TPREL_16_X:
> + Type = ELF::R_HEX_TPREL_16_X;
> + break;
> + case fixup_Hexagon_TPREL_11_X:
> + Type = ELF::R_HEX_TPREL_11_X;
> + break;
> }
> return Type;
> }
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTa
> rgetDesc/HexagonMCTargetDesc.cpp?rev=238748&r1=238747&r2=238748&view=d
> iff
> ======================================================================
> ========
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> +++ Mon Jun 1 09:51:26 2015
> @@ -112,6 +112,10 @@ extern "C" void LLVMInitializeHexagonTar
> TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
> createHexagonMCCodeEmitter);
>
> + // Register the asm backend
> + TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
> + createHexagonAsmBackend);
> +
> // Register the MC Inst Printer
> TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
> createHexagonMCInstPrinter);
>
> Added: llvm/trunk/test/CodeGen/Hexagon/relax.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/re
> lax.ll?rev=238748&view=auto
> ======================================================================
> ========
> --- llvm/trunk/test/CodeGen/Hexagon/relax.ll (added)
> +++ llvm/trunk/test/CodeGen/Hexagon/relax.ll Mon Jun 1 09:51:26 2015
> @@ -0,0 +1,14 @@
> +; RUN: llc -march=hexagon -filetype=obj < %s | llvm-objdump -d -r - |
> +FileCheck %s
> +
> +declare void @bar()
> +
> +define void @foo() {
> +call void @bar()
> +ret void
> +}
> +
> +
> +; CHECK: { allocframe(#0) }
> +; CHECK: { call 0 }
> +; CHECK: 00000004: R_HEX_B22_PCREL
> +; CHECK: { dealloc_return }
> \ No newline at end of file
>
>
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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