[PATCH] [mips][microMIPS] Implement BREAK, EHB and EI instructions

[Daniel Sanders]

================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:229
@@ +228,3 @@
+  let Inst{25-21} = 0x00;
+  let Inst{20-16} = rt;
+  let Inst{15-6}  = funct;
----------------
Nit: It's called 'rs' in the docs.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:260
@@ -251,1 +259,3 @@
 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
+def EHB_MMR6 : R6MMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
+def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
----------------
Shouldn't EHB's R6MMR6Rel be StdMMR6Rel?

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:400-403
@@ -393,1 +399,6 @@
+
+def uimm_opnd10 : Operand<i32> {
+  let ParserMatchClass = MipsUImm10AsmOperand;
+}
+
 def simm16_64   : Operand<i64> {
----------------
Adding a second uimm10 operand is going to get confusing. Please use the existing uimm10 and change that to restrict the accepted immediates like you have here.

I'd recommend changing uimm10 in a separate commit.

================
Comment at: test/MC/Disassembler/Mips/micromips.txt:534-539
@@ -533,1 +533,7 @@
 0x60 0xa4 0xae 0x08
+
+# CHECK: ei
+0x00 0x00 0x57 0x7c
+
+# CHECK: ei $10
+0x00 0x0a 0x57 0x7c
----------------
I know this is from earlier patches, but please change the rest of this file (in a separate commit) to the 
  0x00 0x0a 0x57 0x7c # CHECK: ei $10
style. Could you also do this for the other micromips disassembler tests?

http://reviews.llvm.org/D10090

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