[PATCH] [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructions

[Simon Pilgrim]

Hi andreadb, spatel, chandlerc,

This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it.

As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions.

>From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. 

As with any AMD-only instructions - if you have experience with these, please consider reviewing as we need all the help we can get ;-)

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10146

Files:
  lib/Target/X86/InstPrinter/X86InstComments.cpp
  lib/Target/X86/Utils/X86ShuffleDecode.cpp
  lib/Target/X86/Utils/X86ShuffleDecode.h
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86IntrinsicsInfo.h
  test/CodeGen/X86/vector-shuffle-sse4a.ll

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