[PATCH] [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions

[Jozef Kolek]

LGTM with a few nits.


================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:255
@@ +254,3 @@
+                                    uint64_t Address,
+                                    const void *Decoder);
+
----------------
Align the parameters.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:1136
@@ +1135,3 @@
+                                    uint64_t Address,
+                                    const void *Decoder) {
+  int Offset = SignExtend32<9>(Insn & 0x1ff);
----------------
Align the parameters.

================
Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:771
@@ +770,3 @@
+                      SmallVectorImpl<MCFixup> &Fixups,
+                      const MCSubtargetInfo &STI) const {
+  // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
----------------
Here too, align the parameters.

================
Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h:177
@@ -175,1 +176,3 @@
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
----------------
Here too, align the parameters.

http://reviews.llvm.org/D10119

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