[llvm] r238344 - ARMTargetParser: Normalising build attributes
Renato Golin
renato.golin at linaro.org
Wed May 27 11:15:37 PDT 2015
Author: rengolin
Date: Wed May 27 13:15:37 2015
New Revision: 238344
URL: http://llvm.org/viewvc/llvm-project?rev=238344&view=rev
Log:
ARMTargetParser: Normalising build attributes
Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu
strings are using ARMTargetParser, it's time to make it a bit more conforming
with what the ABI says.
This commit adds some clarification on what build attributes are accepted and
which are "non-standard". It also makes clear that the "defaultCPU" and
"defaultArch" methods were really just build attribute getters.
It also diverges from GCC's behaviour to say that armv2/armv3 are really an
ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4.
Modified:
llvm/trunk/include/llvm/Support/TargetParser.h
llvm/trunk/lib/Support/TargetParser.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/trunk/test/MC/ARM/directive-arch-armv2.s
llvm/trunk/test/MC/ARM/directive-arch-armv2a.s
llvm/trunk/test/MC/ARM/directive-arch-armv3.s
llvm/trunk/test/MC/ARM/directive-arch-armv3m.s
Modified: llvm/trunk/include/llvm/Support/TargetParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetParser.h (original)
+++ llvm/trunk/include/llvm/Support/TargetParser.h Wed May 27 13:15:37 2015
@@ -56,17 +56,19 @@ namespace ARM {
AK_ARMV5,
AK_ARMV5T,
AK_ARMV5TE,
+ AK_ARMV5TEJ,
AK_ARMV6,
- AK_ARMV6J,
AK_ARMV6K,
AK_ARMV6T2,
AK_ARMV6Z,
AK_ARMV6ZK,
AK_ARMV6M,
+ AK_ARMV6SM,
AK_ARMV7,
AK_ARMV7A,
AK_ARMV7R,
AK_ARMV7M,
+ AK_ARMV7EM,
AK_ARMV8A,
AK_ARMV8_1A,
// Non-standard Arch names.
@@ -74,13 +76,11 @@ namespace ARM {
AK_IWMMXT2,
AK_XSCALE,
AK_ARMV5E,
- AK_ARMV5TEJ,
- AK_ARMV6SM,
+ AK_ARMV6J,
AK_ARMV6HL,
AK_ARMV7L,
AK_ARMV7HL,
AK_ARMV7S,
- AK_ARMV7EM,
AK_LAST
};
@@ -133,8 +133,8 @@ public:
// Information by ID
static const char * getFPUName(unsigned FPUKind);
static const char * getArchName(unsigned ArchKind);
- static unsigned getArchDefaultCPUArch(unsigned ArchKind);
- static const char * getArchDefaultCPUName(unsigned ArchKind);
+ static unsigned getArchAttr(unsigned ArchKind);
+ static const char * getCPUAttr(unsigned ArchKind);
static const char * getArchExtName(unsigned ArchExtKind);
static const char * getDefaultCPU(StringRef Arch);
Modified: llvm/trunk/lib/Support/TargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp (original)
+++ llvm/trunk/lib/Support/TargetParser.cpp Wed May 27 13:15:37 2015
@@ -43,48 +43,51 @@ struct {
{ "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
{ "softvfp", ARM::FK_SOFTVFP }
};
-// List of canonical arch names (use getArchSynonym)
+// List of canonical arch names (use getArchSynonym).
+// This table also provides the build attribute fields for CPU arch
+// and Arch ID, according to the Addenda to the ARM ABI, chapters
+// 2.4 and 2.3.5.2 respectively.
// FIXME: TableGen this.
struct {
const char *Name;
ARM::ArchKind ID;
- const char *DefaultCPU;
- ARMBuildAttrs::CPUArch DefaultArch;
+ const char *CPUAttr; // CPU class in build attributes.
+ ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
} ARCHNames[] = {
{ "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
- { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
- { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
- { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
- { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
+ { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::Pre_v4 },
+ { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::Pre_v4 },
+ { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::Pre_v4 },
+ { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::Pre_v4 },
{ "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
{ "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
- { "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
+ { "armv5", ARM::AK_ARMV5, "5T", ARMBuildAttrs::CPUArch::v5T },
{ "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
{ "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
+ { "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", ARMBuildAttrs::CPUArch::v5TEJ },
{ "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
- { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
{ "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
{ "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
{ "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
+ { "armv6s-m", ARM::AK_ARMV6SM, "6S-M", ARMBuildAttrs::CPUArch::v6S_M },
{ "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
// Non-standard Arch names.
{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
{ "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE },
- { "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE },
- { "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE },
- { "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M },
+ { "armv5e", ARM::AK_ARMV5E, "5TE", ARMBuildAttrs::CPUArch::v5TE },
+ { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
{ "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M },
- { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
{ "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 },
- { "armv7hl", ARM::AK_ARMV7HL, "7H-L", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7hl", ARM::AK_ARMV7HL, "7-L", ARMBuildAttrs::CPUArch::v7 },
{ "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 }
};
// List of canonical ARCH names (use getARCHSynonym)
@@ -211,16 +214,16 @@ const char *ARMTargetParser::getArchName
return ARCHNames[ArchKind].Name;
}
-const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
+const char *ARMTargetParser::getCPUAttr(unsigned ArchKind) {
if (ArchKind >= ARM::AK_LAST)
return nullptr;
- return ARCHNames[ArchKind].DefaultCPU;
+ return ARCHNames[ArchKind].CPUAttr;
}
-unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
+unsigned ARMTargetParser::getArchAttr(unsigned ArchKind) {
if (ArchKind >= ARM::AK_LAST)
return ARMBuildAttrs::CPUArch::Pre_v4;
- return ARCHNames[ArchKind].DefaultArch;
+ return ARCHNames[ArchKind].ArchAttr;
}
const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
@@ -266,6 +269,7 @@ StringRef ARMTargetParser::getFPUSynonym
StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
return StringSwitch<StringRef>(Arch)
+ .Cases("armv6sm", "v6sm", "armv6s-m")
.Cases("armv6m", "v6m", "armv6-m")
.Cases("armv7a", "v7a", "armv7-a")
.Cases("armv7r", "v7r", "armv7-r")
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp Wed May 27 13:15:37 2015
@@ -688,16 +688,16 @@ void ARMTargetELFStreamer::emitArchDefau
using namespace ARMBuildAttrs;
setAttributeItem(CPU_name,
- ARMTargetParser::getArchDefaultCPUName(Arch),
+ ARMTargetParser::getCPUAttr(Arch),
false);
if (EmittedArch == ARM::AK_INVALID)
setAttributeItem(CPU_arch,
- ARMTargetParser::getArchDefaultCPUArch(Arch),
+ ARMTargetParser::getArchAttr(Arch),
false);
else
setAttributeItem(CPU_arch,
- ARMTargetParser::getArchDefaultCPUArch(EmittedArch),
+ ARMTargetParser::getArchAttr(EmittedArch),
false);
switch (Arch) {
Modified: llvm/trunk/test/MC/ARM/directive-arch-armv2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv2.s?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv2.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv2.s Wed May 27 13:15:37 2015
@@ -20,7 +20,7 @@
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: ARM v4
+@ CHECK-ATTR: Description: Pre-v4
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: ARM_ISA_use
Modified: llvm/trunk/test/MC/ARM/directive-arch-armv2a.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv2a.s?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv2a.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv2a.s Wed May 27 13:15:37 2015
@@ -20,7 +20,7 @@
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: ARM v4
+@ CHECK-ATTR: Description: Pre-v4
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: ARM_ISA_use
Modified: llvm/trunk/test/MC/ARM/directive-arch-armv3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv3.s?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv3.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv3.s Wed May 27 13:15:37 2015
@@ -20,7 +20,7 @@
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: ARM v4
+@ CHECK-ATTR: Description: Pre-v4
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: ARM_ISA_use
Modified: llvm/trunk/test/MC/ARM/directive-arch-armv3m.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/directive-arch-armv3m.s?rev=238344&r1=238343&r2=238344&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/directive-arch-armv3m.s (original)
+++ llvm/trunk/test/MC/ARM/directive-arch-armv3m.s Wed May 27 13:15:37 2015
@@ -20,7 +20,7 @@
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: CPU_arch
-@ CHECK-ATTR: Description: ARM v4
+@ CHECK-ATTR: Description: Pre-v4
@ CHECK-ATTR: }
@ CHECK-ATTR: Attribute {
@ CHECK-ATTR: TagName: ARM_ISA_use
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