[llvm] r238228 - R600: Add comments to subword private address load lowering code
Jan Vesely
jan.vesely at rutgers.edu
Tue May 26 11:07:21 PDT 2015
Author: jvesely
Date: Tue May 26 13:07:21 2015
New Revision: 238228
URL: http://llvm.org/viewvc/llvm-project?rev=238228&view=rev
Log:
R600: Add comments to subword private address load lowering code
v2: Use C++ comments and end with periods
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Modified:
llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=238228&r1=238227&r2=238228&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Tue May 26 13:07:21 2015
@@ -1451,22 +1451,34 @@ SDValue AMDGPUTargetLowering::LowerLOAD(
ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
return SDValue();
+ // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
+ // register (2-)byte extract.
+ // Get Register holding the target.
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
DAG.getConstant(2, DL, MVT::i32));
+ // Load the Register.
SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
Load->getChain(), Ptr,
DAG.getTargetConstant(0, DL, MVT::i32),
Op.getOperand(2));
+
+ // Get offset within the register.
SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
Load->getBasePtr(),
DAG.getConstant(0x3, DL, MVT::i32));
+
+ // Bit offset of target byte (byteIdx * 8).
SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
DAG.getConstant(3, DL, MVT::i32));
+ // Shift to the right.
Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
+ // Eliminate the upper bits by setting them to ...
EVT MemEltVT = MemVT.getScalarType();
+
+ // ... ones.
if (ExtType == ISD::SEXTLOAD) {
SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
@@ -1478,6 +1490,7 @@ SDValue AMDGPUTargetLowering::LowerLOAD(
return DAG.getMergeValues(Ops, DL);
}
+ // ... or zeros.
SDValue Ops[] = {
DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
Load->getChain()
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