[llvm] r238032 - [PPC64] Add support for clrbhrb, mfbhrbe, rfebb.
Bill Schmidt
wschmidt at linux.vnet.ibm.com
Fri May 22 09:44:11 PDT 2015
Author: wschmidt
Date: Fri May 22 11:44:10 2015
New Revision: 238032
URL: http://llvm.org/viewvc/llvm-project?rev=238032&view=rev
Log:
[PPC64] Add support for clrbhrb, mfbhrbe, rfebb.
This patch adds support for the ISA 2.07 additions involving the
branch history rolling buffer and event-based branching. These will
not be used by typical applications, so built-in support is not
required. They will only be available via inline assembly.
Assembly/disassembly tests are included in the patch.
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Fri May 22 11:44:10 2015
@@ -460,6 +460,8 @@ public:
bool isU8ImmX8() const { return Kind == Immediate &&
isUInt<8>(getImm()) &&
(getImm() & 7) == 0; }
+
+ bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
bool isU16Imm() const {
switch (Kind) {
Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Fri May 22 11:44:10 2015
@@ -299,6 +299,13 @@ void PPCInstPrinter::printU6ImmOperand(c
O << (unsigned int)Value;
}
+void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ unsigned short Value = MI->getOperand(OpNo).getImm();
+ assert(Value <= 1023 && "Invalid u10imm argument!");
+ O << (unsigned short)Value;
+}
+
void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned short Value = MI->getOperand(OpNo).getImm();
Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original)
+++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Fri May 22 11:44:10 2015
@@ -55,6 +55,7 @@ public:
void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri May 22 11:44:10 2015
@@ -1048,6 +1048,9 @@ const char *PPCTargetLowering::getTarget
case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
case PPCISD::SC: return "PPCISD::SC";
+ case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
+ case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
+ case PPCISD::RFEBB: return "PPCISD::RFEBB";
case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Fri May 22 11:44:10 2015
@@ -275,6 +275,16 @@ namespace llvm {
/// operand identifies the operating system entry point.
SC,
+ /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
+ CLRBHRB,
+
+ /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
+ /// history rolling buffer entry.
+ MFBHRBE,
+
+ /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
+ RFEBB,
+
/// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
/// endian. Maps to an xxswapd instruction that corrects an lxvd2x
/// or stxvd2x instruction. The chain is necessary because the
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Fri May 22 11:44:10 2015
@@ -1080,6 +1080,19 @@ class XLForm_4<bits<6> opcode, bits<10>
let Inst{31} = RC;
}
+class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<1> S;
+
+ let Pattern = pattern;
+
+ let Inst{6-19} = 0;
+ let Inst{20} = S;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
bits<6> opcode2, bits<2> xo2,
dag OOL, dag IOL, string asmstr,
@@ -1157,6 +1170,19 @@ class XFXForm_3<bits<6> opcode, bits<10>
let Inst{21-30} = xo;
let Inst{31} = 0;
}
+
+class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<5> RT;
+ bits<10> Entry;
+ let Pattern = pattern;
+
+ let Inst{6-10} = RT;
+ let Inst{11-20} = Entry;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri May 22 11:44:10 2015
@@ -201,6 +201,12 @@ def SDT_PPCsc : SDTypeProfile<0, 1,
def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
[SDNPHasChain, SDNPSideEffect]>;
+def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone,
+ [SDNPHasChain, SDNPSideEffect]>;
+def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
+def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
+ [SDNPHasChain, SDNPSideEffect]>;
+
def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
@@ -499,6 +505,15 @@ def u6imm : Operand<i32> {
let ParserMatchClass = PPCU6ImmAsmOperand;
let DecoderMethod = "decodeUImmOperand<6>";
}
+def PPCU10ImmAsmOperand : AsmOperandClass {
+ let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
+ let RenderMethod = "addImmOperands";
+}
+def u10imm : Operand<i32> {
+ let PrintMethod = "printU10ImmOperand";
+ let ParserMatchClass = PPCU10ImmAsmOperand;
+ let DecoderMethod = "decodeUImmOperand<10>";
+}
def PPCU12ImmAsmOperand : AsmOperandClass {
let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
let RenderMethod = "addImmOperands";
@@ -1357,6 +1372,24 @@ let PPC970_Unit = 7 in {
"sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
}
+// Branch history rolling buffer.
+def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
+ [(PPCclrbhrb)]>,
+ PPC970_DGroup_Single;
+// The $dmy argument used for MFBHRBE is not needed; however, including
+// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
+// interferes with necessary special handling (see PPCFastISel.cpp).
+def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
+ (ins u10imm:$imm, u10imm:$dmy),
+ "mfbhrbe $rD, $imm", IIC_BrB,
+ [(set i32:$rD,
+ (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
+ PPC970_DGroup_First;
+
+def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
+ IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
+ PPC970_DGroup_Single;
+
// DCB* instructions.
def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt Fri May 22 11:44:10 2015
@@ -73,6 +73,15 @@
# CHECK: sc
0x44 0x00 0x00 0x02
+# CHECK: clrbhrb
+0x7c 0x00 0x03 0x5c
+
+# CHECK: mfbhrbe 9, 983
+0x7d 0x3e 0xba 0x5c
+
+# CHECK: rfebb 1
+0x4c 0x00 0x09 0x24
+
# CHECK: lbz 2, 128(4)
0x88 0x44 0x00 0x80
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding.s?rev=238032&r1=238031&r2=238032&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding.s Fri May 22 11:44:10 2015
@@ -112,6 +112,18 @@
# CHECK-LE: sc # encoding: [0x02,0x00,0x00,0x44]
sc
+# Branch history rolling buffer
+
+# CHECK-BE: clrbhrb # encoding: [0x7c,0x00,0x03,0x5c]
+# CHECK-LE: clrbhrb # encoding: [0x5c,0x03,0x00,0x7c]
+ clrbhrb
+# CHECK-BE: mfbhrbe 9, 983 # encoding: [0x7d,0x3e,0xba,0x5c]
+# CHECK-LE: mfbhrbe 9, 983 # encoding: [0x5c,0xba,0x3e,0x7d]
+ mfbhrbe 9, 983
+# CHECK-BE: rfebb 1 # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-LE: rfebb 1 # encoding: [0x24,0x09,0x00,0x4c]
+ rfebb 1
+
# Fixed-point facility
# Fixed-point load instructions
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