[PATCH] Adjust the cost of vectorized SHL/SRL/SRA

[Arnold Schwaighofer]

I share Simon's concerns. Please make sure that we still get a good estimate for kernels like (these are from the rdar mentioned in the commit).

  #define TYPE char
  #define OP >>
  #define SIZE 1024
  #define TYPE_ALIGN __attribute__((aligned(16)))
  
  TYPE A1[SIZE] TYPE_ALIGN;
  TYPE B1[SIZE] TYPE_ALIGN;
  TYPE C1[SIZE] TYPE_ALIGN;
  
  void kernel1() {
    for (int i = 0; i < SIZE; ++i) {
      A1[i] = B1[i] OP C1[i];
  }

or:

  for(k=0, r=0; k<pos; k++)
    r += (MAX_UNSIGNED) 1 << k;


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D9923

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/