[llvm] r237685 - [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Tue May 19 04:21:37 PDT 2015
Author: zjovanovic
Date: Tue May 19 06:21:37 2015
New Revision: 237685
URL: http://llvm.org/viewvc/llvm-project?rev=237685&view=rev
Log:
[mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions
Differential Revision: http://reviews.llvm.org/D8769
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=237685&r1=237684&r2=237685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Tue May 19 06:21:37 2015
@@ -30,10 +30,14 @@ class BITSWAP_MMR6_ENC : POOL32A_BITSWAP
class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
+class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
+class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
+class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
+class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
@@ -190,6 +194,10 @@ class SELEQNE_Z_MMR6_DESC_BASE<string in
class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
+class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
+class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
+class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
+class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
//===----------------------------------------------------------------------===//
//
@@ -215,10 +223,14 @@ def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MM
def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
+def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
+def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
+def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
+def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=237685&r1=237684&r2=237685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Tue May 19 06:21:37 2015
@@ -415,7 +415,8 @@ class BITSWAP_DESC_BASE<string instr_asm
class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- SDPatternOperator Op=null_frag> {
+ SDPatternOperator Op=null_frag>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
@@ -689,8 +690,8 @@ def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
-def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
-def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
+def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
+def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
@@ -710,8 +711,8 @@ def MINA_D : MINA_D_ENC, MINA_D_DESC, I
def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
-def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
+def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
+def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=237685&r1=237684&r2=237685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Tue May 19 06:21:37 2015
@@ -32,6 +32,10 @@
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
+
+0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
+
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
@@ -40,6 +44,10 @@
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 3
+0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
+
+0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
+
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=237685&r1=237684&r2=237685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue May 19 06:21:37 2015
@@ -15,10 +15,14 @@
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
+ div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
+ divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x26,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
+ mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
+ modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
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