[llvm] r237478 - Move some methods to a new MCInstrDesc.cpp file to allow includes to be trimmed. NFC.
Pete Cooper
peter_cooper at apple.com
Fri May 15 14:29:44 PDT 2015
Author: pete
Date: Fri May 15 16:29:43 2015
New Revision: 237478
URL: http://llvm.org/viewvc/llvm-project?rev=237478&view=rev
Log:
Move some methods to a new MCInstrDesc.cpp file to allow includes to be trimmed. NFC.
MCInstrDesc.h includes things like MCInst.h which i can now remove after this. That will be a future commit.
Reviewed by Jim Grosbach.
Added:
llvm/trunk/lib/MC/MCInstrDesc.cpp
Modified:
llvm/trunk/include/llvm/MC/MCInstrDesc.h
llvm/trunk/lib/MC/CMakeLists.txt
Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=237478&r1=237477&r2=237478&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Fri May 15 16:29:43 2015
@@ -165,16 +165,7 @@ public:
/// \brief Returns true if a certain instruction is deprecated and if so
/// returns the reason in \p Info.
bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
- std::string &Info) const {
- if (ComplexDeprecationInfo)
- return ComplexDeprecationInfo(MI, STI, Info);
- if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
- // FIXME: it would be nice to include the subtarget feature here.
- Info = "deprecated";
- return true;
- }
- return false;
- }
+ std::string &Info) const;
/// \brief Return the opcode number for this descriptor.
unsigned getOpcode() const { return Opcode; }
@@ -257,25 +248,7 @@ public:
/// \brief Return true if this is a branch or an instruction which directly
/// writes to the program counter. Considered 'may' affect rather than
/// 'does' affect as things like predication are not taken into account.
- bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
- if (isBranch() || isCall() || isReturn() || isIndirectBranch())
- return true;
- unsigned PC = RI.getProgramCounter();
- if (PC == 0)
- return false;
- if (hasDefOfPhysReg(MI, PC, RI))
- return true;
- // A variadic instruction may define PC in the variable operand list.
- // There's currently no indication of which entries in a variable
- // list are defs and which are uses. While that's the case, this function
- // needs to assume they're defs in order to be conservatively correct.
- for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
- if (MI.getOperand(i).isReg() &&
- RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
- return true;
- }
- return false;
- }
+ bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
/// \brief Return true if this instruction has a predicate operand
/// that controls execution. It may be set to 'always', or may be set to other
@@ -532,24 +505,7 @@ public:
/// \brief Return true if this instruction implicitly
/// defines the specified physical register.
bool hasImplicitDefOfPhysReg(unsigned Reg,
- const MCRegisterInfo *MRI = nullptr) const {
- if (const uint16_t *ImpDefs = ImplicitDefs)
- for (; *ImpDefs; ++ImpDefs)
- if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
- return true;
- return false;
- }
-
- /// \brief Return true if this instruction defines the specified physical
- /// register, either explicitly or implicitly.
- bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
- const MCRegisterInfo &RI) const {
- for (int i = 0, e = NumDefs; i != e; ++i)
- if (MI.getOperand(i).isReg() &&
- RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
- return true;
- return hasImplicitDefOfPhysReg(Reg, &RI);
- }
+ const MCRegisterInfo *MRI = nullptr) const;
/// \brief Return the scheduling class for this instruction. The
/// scheduling class is an index into the InstrItineraryData table. This
@@ -572,6 +528,13 @@ public:
}
return -1;
}
+
+private:
+
+ /// \brief Return true if this instruction defines the specified physical
+ /// register, either explicitly or implicitly.
+ bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
+ const MCRegisterInfo &RI) const;
};
} // end namespace llvm
Modified: llvm/trunk/lib/MC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=237478&r1=237477&r2=237478&view=diff
==============================================================================
--- llvm/trunk/lib/MC/CMakeLists.txt (original)
+++ llvm/trunk/lib/MC/CMakeLists.txt Fri May 15 16:29:43 2015
@@ -19,6 +19,7 @@ add_llvm_library(LLVMMC
MCInst.cpp
MCInstPrinter.cpp
MCInstrAnalysis.cpp
+ MCInstrDesc.cpp
MCLabel.cpp
MCLinkerOptimizationHint.cpp
MCMachOStreamer.cpp
Added: llvm/trunk/lib/MC/MCInstrDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCInstrDesc.cpp?rev=237478&view=auto
==============================================================================
--- llvm/trunk/lib/MC/MCInstrDesc.cpp (added)
+++ llvm/trunk/lib/MC/MCInstrDesc.cpp Fri May 15 16:29:43 2015
@@ -0,0 +1,68 @@
+//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCInst.h"
+
+using namespace llvm;
+
+bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
+ std::string &Info) const {
+ if (ComplexDeprecationInfo)
+ return ComplexDeprecationInfo(MI, STI, Info);
+ if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
+ // FIXME: it would be nice to include the subtarget feature here.
+ Info = "deprecated";
+ return true;
+ }
+ return false;
+}
+bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
+ const MCRegisterInfo &RI) const {
+ if (isBranch() || isCall() || isReturn() || isIndirectBranch())
+ return true;
+ unsigned PC = RI.getProgramCounter();
+ if (PC == 0)
+ return false;
+ if (hasDefOfPhysReg(MI, PC, RI))
+ return true;
+ // A variadic instruction may define PC in the variable operand list.
+ // There's currently no indication of which entries in a variable
+ // list are defs and which are uses. While that's the case, this function
+ // needs to assume they're defs in order to be conservatively correct.
+ for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
+ if (MI.getOperand(i).isReg() &&
+ RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
+ return true;
+ }
+ return false;
+}
+
+bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
+ const MCRegisterInfo *MRI) const {
+ if (const uint16_t *ImpDefs = ImplicitDefs)
+ for (; *ImpDefs; ++ImpDefs)
+ if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
+ return true;
+ return false;
+}
+
+bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
+ const MCRegisterInfo &RI) const {
+ for (int i = 0, e = NumDefs; i != e; ++i)
+ if (MI.getOperand(i).isReg() &&
+ RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
+ return true;
+ return hasImplicitDefOfPhysReg(Reg, &RI);
+}
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