[llvm] r237428 - [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.

[Toma Tabacu]

Author: tomatabacu
Date: Fri May 15 04:42:11 2015
New Revision: 237428

URL: http://llvm.org/viewvc/llvm-project?rev=237428&view=rev
Log:
[mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.

Summary:
To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI.
This currently happens because of sign extension.

To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8662

Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-expansions.s
    llvm/trunk/test/MC/Mips/mips64-expansions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=237428&r1=237427&r2=237428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Fri May 15 04:42:11 2015
@@ -1758,7 +1758,7 @@ bool MipsAsmParser::loadImmediate(int64_
     tmpInst.addOperand(MCOperand::createReg(SrcReg));
     tmpInst.addOperand(MCOperand::createImm(ImmValue));
     Instructions.push_back(tmpInst);
-  } else if ((ImmValue & 0xffffffff) == ImmValue) {
+  } else if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
     if (!AssemblerOptions.back()->isMacro())
       Warning(IDLoc, "macro instruction expanded into multiple instructions");
 
@@ -1768,10 +1768,23 @@ bool MipsAsmParser::loadImmediate(int64_
     uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
     uint16_t Bits15To0 = ImmValue & 0xffff;
 
-    tmpInst.setOpcode(Mips::LUi);
-    tmpInst.addOperand(MCOperand::createReg(DstReg));
-    tmpInst.addOperand(MCOperand::createImm(Bits31To16));
-    Instructions.push_back(tmpInst);
+    if (!Is32BitImm && !isInt<32>(ImmValue)) {
+      // For DLI, expand to an ORi instead of a LUi to avoid sign-extending the
+      // upper 32 bits.
+      tmpInst.setOpcode(Mips::ORi);
+      tmpInst.addOperand(MCOperand::createReg(DstReg));
+      tmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      tmpInst.addOperand(MCOperand::createImm(Bits31To16));
+      tmpInst.setLoc(IDLoc);
+      Instructions.push_back(tmpInst);
+      // Move the value to the upper 16 bits by doing a 16-bit left shift.
+      createLShiftOri<16>(0, DstReg, IDLoc, Instructions);
+    } else {
+      tmpInst.setOpcode(Mips::LUi);
+      tmpInst.addOperand(MCOperand::createReg(DstReg));
+      tmpInst.addOperand(MCOperand::createImm(Bits31To16));
+      Instructions.push_back(tmpInst);
+    }
     createLShiftOri<0>(Bits15To0, DstReg, IDLoc, Instructions);
 
     if (UseSrcReg)

Modified: llvm/trunk/test/MC/Mips/mips-expansions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-expansions.s?rev=237428&r1=237427&r2=237428&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-expansions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-expansions.s Fri May 15 04:42:11 2015
@@ -11,6 +11,8 @@
 # CHECK:     addiu   $8, $zero, -8    # encoding: [0xf8,0xff,0x08,0x24]
 # CHECK:     lui     $9, 1            # encoding: [0x01,0x00,0x09,0x3c]
 # CHECK-NOT: ori $9, $9, 0            # encoding: [0x00,0x00,0x29,0x35]
+# CHECK:     lui     $10, 65519       # encoding: [0xef,0xff,0x0a,0x3c]
+# CHECK:     ori     $10, $10, 61423  # encoding: [0xef,0xef,0x4a,0x35]
 
 # CHECK: ori     $4, $zero, 20       # encoding: [0x14,0x00,0x04,0x34]
 # CHECK: lui     $7, 1               # encoding: [0x01,0x00,0x07,0x3c]
@@ -61,6 +63,7 @@
     li $7,65538
     li $8, ~7
     li $9, 0x10000
+    li $10, ~(0x101010)
 
     la $a0, 20
     la $7,65538

Modified: llvm/trunk/test/MC/Mips/mips64-expansions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-expansions.s?rev=237428&r1=237427&r2=237428&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64-expansions.s (original)
+++ llvm/trunk/test/MC/Mips/mips64-expansions.s Fri May 15 04:42:11 2015
@@ -178,3 +178,18 @@
 # CHECK: ori    $8, $8, 65534       # encoding: [0xfe,0xff,0x08,0x35]
 # CHECK: dsll   $8, $8, 16          # encoding: [0x38,0x44,0x08,0x00]
 # CHECK: ori    $8, $8, 65535       # encoding: [0xff,0xff,0x08,0x35]
+
+# Check that signed negative 32-bit immediates are loaded correctly:
+  li $10, ~(0x101010)
+# CHECK: lui $10, 65519        # encoding: [0xef,0xff,0x0a,0x3c]
+# CHECK: ori $10, $10, 61423   # encoding: [0xef,0xef,0x4a,0x35]
+# CHECK-NOT: dsll
+
+  dli $10, ~(0x202020)
+# CHECK: lui $10, 65503        # encoding: [0xdf,0xff,0x0a,0x3c]
+# CHECK: ori $10, $10, 57311   # encoding: [0xdf,0xdf,0x4a,0x35]
+# CHECK-NOT: dsll
+
+  dli $9, 0x80000000
+# CHECK: ori  $9, $zero, 32768 # encoding: [0x00,0x80,0x09,0x34]
+# CHECK: dsll $9, $9, 16       # encoding: [0x38,0x4c,0x09,0x00]