[PATCH] [SDAG] Add SDNodes for umin, umax, smin and smax

[James Molloy]

Hi Elena,

Updated according to comments. I changed the check - we still need to check that all the VTs are the same, otherwise the transformation would be completely incorrect.

The while statement can't be moved inside the if, because the while statement modifies "VT". The aim is to peel off SplitVector operations and suchlike until we get to the bottommost type, which we then check if it's legal or custom.

Cheers,

James


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D9746

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/CodeGen/TargetLoweringBase.cpp

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