[llvm] r237341 - [TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC.

[Craig Topper]

Author: ctopper
Date: Thu May 14 00:53:56 2015
New Revision: 237341

URL: http://llvm.org/viewvc/llvm-project?rev=237341&view=rev
Log:
[TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC.

Modified:
    llvm/trunk/include/llvm/TableGen/Record.h
    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp

Modified: llvm/trunk/include/llvm/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/TableGen/Record.h?rev=237341&r1=237340&r2=237341&view=diff
==============================================================================
--- llvm/trunk/include/llvm/TableGen/Record.h (original)
+++ llvm/trunk/include/llvm/TableGen/Record.h Thu May 14 00:53:56 2015
@@ -842,7 +842,6 @@ public:
   inline const_iterator begin() const { return Values.begin(); }
   inline const_iterator end  () const { return Values.end();   }
 
-  inline size_t         size () const { return Values.size();  }
   inline bool           empty() const { return Values.empty(); }
 
   /// resolveListElementReference - This method is used to implement

Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=237341&r1=237340&r2=237341&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu May 14 00:53:56 2015
@@ -676,7 +676,7 @@ CodeGenRegisterClass::CodeGenRegisterCla
   // Allocation order 0 is the full set. AltOrders provides others.
   const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
   ListInit *AltOrders = R->getValueAsListInit("AltOrders");
-  Orders.resize(1 + AltOrders->size());
+  Orders.resize(1 + AltOrders->getSize());
 
   // Default allocation order always contains all registers.
   for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
@@ -689,7 +689,7 @@ CodeGenRegisterClass::CodeGenRegisterCla
 
   // Alternative allocation orders may be subsets.
   SetTheory::RecSet Order;
-  for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
+  for (unsigned i = 0, e = AltOrders->getSize(); i != e; ++i) {
     RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
     Orders[1 + i].append(Order.begin(), Order.end());
     // Verify that all altorder members are regclass members.