[llvm] r237293 - ARM: refactor optimizeThumb2JumpTables.
Tim Northover
tnorthover at apple.com
Wed May 13 13:28:32 PDT 2015
Author: tnorthover
Date: Wed May 13 15:28:32 2015
New Revision: 237293
URL: http://llvm.org/viewvc/llvm-project?rev=237293&view=rev
Log:
ARM: refactor optimizeThumb2JumpTables.
The previous logic mixed 2 separate questions:
+ Can we form a TBB/TBH instruction?
+ Can we remove the jump-table calculation before it?
It then performed a bunch of random tests on the instructions earlier in the
basic block, which were probably sufficient to answer 2 but only because of the
very limited ways in which a t2BR_JT can actually be created.
For example there's no reason to expect the LeaInst to define the same base
register as the following indexing calulation. In practice this means we might
have missed opportunities to form TBB/TBH, in theory you could end up
misidentifying a sequence and removing the wrong LEA:
%R1 = t2LEApcrelJT ...
%R2 = t2LEApcrelJT ...
<... using and killing %R2 ...>
%R2 = t2ADDr %R1, $Ridx
Before we would have looked for an LEA defining %R2 and found the wrong one. We
just got lucky that jump table setup was (almost?) always confined to a single
basic block and there was only one jump table per block.
Modified:
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=237293&r1=237292&r2=237293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed May 13 15:28:32 2015
@@ -301,6 +301,8 @@ namespace {
bool optimizeThumb2Instructions();
bool optimizeThumb2Branches();
bool reorderThumb2JumpTables();
+ unsigned removeDeadDefinitions(MachineInstr *MI, unsigned BaseReg,
+ unsigned IdxReg);
bool optimizeThumb2JumpTables();
MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB,
MachineBasicBlock *JTBB);
@@ -1842,6 +1844,79 @@ bool ARMConstantIslands::optimizeThumb2B
return MadeChange;
}
+/// If we've formed a TBB or TBH instruction, the base register is now
+/// redundant. In most cases, the instructions defining it will now be dead and
+/// can be tidied up. This function removes them if so, and returns the number
+/// of bytes saved.
+unsigned ARMConstantIslands::removeDeadDefinitions(MachineInstr *MI,
+ unsigned BaseReg,
+ unsigned IdxReg) {
+ unsigned BytesRemoved = 0;
+ MachineBasicBlock *MBB = MI->getParent();
+
+ // Scan backwards to find the instruction that defines the base
+ // register. Due to post-RA scheduling, we can't count on it
+ // immediately preceding the branch instruction.
+ MachineBasicBlock::iterator PrevI = MI;
+ MachineBasicBlock::iterator B = MBB->begin();
+ while (PrevI != B && !PrevI->definesRegister(BaseReg))
+ --PrevI;
+
+ // If for some reason we didn't find it, we can't do anything, so
+ // just skip this one.
+ if (!PrevI->definesRegister(BaseReg) || PrevI->hasUnmodeledSideEffects() ||
+ PrevI->mayStore())
+ return BytesRemoved;
+
+ MachineInstr *AddrMI = PrevI;
+ unsigned NewBaseReg = BytesRemoved;
+
+ // Examine the instruction that calculates the jumptable entry address. Make
+ // sure it only defines the base register and kills any uses other than the
+ // index register. We also need precisely one use to trace backwards to
+ // (hopefully) the LEA.
+ for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
+ const MachineOperand &MO = AddrMI->getOperand(k);
+ if (!MO.isReg() || !MO.getReg())
+ continue;
+ if (MO.isDef() && MO.getReg() != BaseReg)
+ return BytesRemoved;
+
+ if (MO.isUse() && MO.getReg() != IdxReg) {
+ if (!MO.isKill() || (NewBaseReg != 0 && NewBaseReg != MO.getReg()))
+ return BytesRemoved;
+ NewBaseReg = MO.getReg();
+ }
+ }
+
+ // Want to continue searching for AddrMI, but there are 2 problems: AddrMI is
+ // going away soon, and even decrementing once may be invalid.
+ if (PrevI != B)
+ PrevI = std::prev(PrevI);
+
+ DEBUG(dbgs() << "remove addr: " << *AddrMI);
+ BytesRemoved += TII->GetInstSizeInBytes(AddrMI);
+ AddrMI->eraseFromParent();
+
+ // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
+ // that gave us the initial base register definition.
+ for (; PrevI != B && !PrevI->definesRegister(NewBaseReg); --PrevI)
+ ;
+
+ // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
+ // to delete it as well.
+ MachineInstr *LeaMI = PrevI;
+ if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
+ LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
+ LeaMI->getOperand(0).getReg() != NewBaseReg)
+ return BytesRemoved;
+
+ DEBUG(dbgs() << "remove lea: " << *LeaMI);
+ BytesRemoved += TII->GetInstSizeInBytes(LeaMI);
+ LeaMI->eraseFromParent();
+ return BytesRemoved;
+}
+
/// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
/// jumptables when it's possible.
bool ARMConstantIslands::optimizeThumb2JumpTables() {
@@ -1889,58 +1964,7 @@ bool ARMConstantIslands::optimizeThumb2J
unsigned IdxReg = MI->getOperand(1).getReg();
bool IdxRegKill = MI->getOperand(1).isKill();
- // Scan backwards to find the instruction that defines the base
- // register. Due to post-RA scheduling, we can't count on it
- // immediately preceding the branch instruction.
- MachineBasicBlock::iterator PrevI = MI;
- MachineBasicBlock::iterator B = MBB->begin();
- while (PrevI != B && !PrevI->definesRegister(BaseReg))
- --PrevI;
-
- // If for some reason we didn't find it, we can't do anything, so
- // just skip this one.
- if (!PrevI->definesRegister(BaseReg))
- continue;
-
- MachineInstr *AddrMI = PrevI;
- bool OptOk = true;
- // Examine the instruction that calculates the jumptable entry address.
- // Make sure it only defines the base register and kills any uses
- // other than the index register.
- for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
- const MachineOperand &MO = AddrMI->getOperand(k);
- if (!MO.isReg() || !MO.getReg())
- continue;
- if (MO.isDef() && MO.getReg() != BaseReg) {
- OptOk = false;
- break;
- }
- if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
- OptOk = false;
- break;
- }
- }
- if (!OptOk)
- continue;
-
- // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
- // that gave us the initial base register definition.
- for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
- ;
-
- // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
- // to delete it as well.
- MachineInstr *LeaMI = PrevI;
- if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
- LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
- LeaMI->getOperand(0).getReg() != BaseReg)
- OptOk = false;
-
- if (!OptOk)
- continue;
-
- DEBUG(dbgs() << "Shrink JT: " << *MI << " addr: " << *AddrMI
- << " lea: " << *LeaMI);
+ DEBUG(dbgs() << "Shrink JT: " << *MI);
unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
MachineBasicBlock::iterator MI_JT = MI;
MachineInstr *NewJTMI =
@@ -1952,15 +1976,11 @@ bool ARMConstantIslands::optimizeThumb2J
// FIXME: Insert an "ALIGN" instruction to ensure the next instruction
// is 2-byte aligned. For now, asm printer will fix it up.
unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
- unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
- OrigSize += TII->GetInstSizeInBytes(LeaMI);
- OrigSize += TII->GetInstSizeInBytes(MI);
-
- AddrMI->eraseFromParent();
- LeaMI->eraseFromParent();
+ unsigned OrigSize = TII->GetInstSizeInBytes(MI);
+ unsigned DeadSize = removeDeadDefinitions(MI, BaseReg, IdxReg);
MI->eraseFromParent();
- int delta = OrigSize - NewSize;
+ int delta = OrigSize - NewSize + DeadSize;
BBInfo[MBB->getNumber()].Size -= delta;
adjustBBOffsetsAfter(MBB);
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